dbgbus
A collection of debugging busses developed and presented at zipcpu.com (by ZipCPU)
qspiflash
A set of Wishbone Controlled SPI Flash Controllers (by ZipCPU)
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
dbgbus
Posts with mentions or reviews of dbgbus.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-01-10.
-
AXI Quad SPI 3.2 Flash programming scripts
I've got a couple different encodings I use to push data over the serial port. Here's the hexbus encoding for example, although I more often use the WBUBUS encoding which you can find attached to many of my projects. They're all based around what I call a "debugging bus" and a "devbus interface". It's really easy to use--once you have it set up.
-
Need help with Objcopy for Verilog Hex File
As examples: - Here's how I process libelf to provide me with an array of section pointers, each containing the address to load the values at - Here's where I then load the values into my design when I'm using an external loader via a debugging bus. - Here's another copy of the same, this time running from within Verilator rather than from within externally controlled logic.
-
How can I get Verilator to Prompt for User Input?
The core component to the single simulated to TCP port can be found here, in uartsim.cpp. You can find a companion software program that will forward the same TCP port to a hardware serial port here, under the name netuart.cpp.
-
CPU DESIGN
There are also open source versions of many of the pieces you will need. I now use an open source crossbar interconnect for most of my designs. I use AutoFPGA to connect all the pieces together. I mentioned my flash controller above, but I also have a SD Card controller I've used quite successfully. I've also posted a UART to Wishbone bridge and discussed network debugging, both of which I use routinely with the ZipCPU. If for no other reason, these components allow me to load or update software on my CPU even after it's been placed into an FPGA. Of course, many of those components are tied to a Wishbone bus infrastructure. You may find you need a bridge of some type to connect different buses structures together--memory naturally tends to operate at one width and clock, video at another, and your CPU at another, so it helps at times to have a universal bus adapter kit handy.
-
Bidirectional AXI data channel
My personal solution to this problem has been to convert bus commands to UART commands. In my world, however, the PC/host sets up the UART commands and the FPGA decodes them into bus commands and then encodes a return value. This is useful because it can be done in 2 wires. I've also done it for JTAG (similar to SPI as implemented) where it takes 4 wires. Check out my articles on the "debugging bus" if you'd like to read more about this approach. (I now have AXI drivers for my debugging bus as well.)
qspiflash
Posts with mentions or reviews of qspiflash.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-11.
-
C++ Verification Testbench Best-Practice Resources?
I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.
-
Simulating peripheral devices in testbenches
I have published, on GitHub, a C++ SPI (and Dual SPI, Quad SPI, etc.) model that I use extensively with Verilator. It's held nicely against all of the flash devices I've had to work with when using Xilinx chips, with a bit of an exception for Micron's delay between the Quad SPI address and any returned data. I also wrote an article about how to design, and then formally verify an SPI flash controller. Feel free to check them out and see if they'll work for you.
-
QUAD SPI Flash Custom Board Pt 2
Since I don't use the Xilinx IP, I've found myself doing this often on any board bringup. You can find my flash IP here, and the software I use to get the flash ID here.
-
AXI Quad SPI 3.2 Flash programming scripts
Here's the flash controller repo I use. There's a flash controller in there for SPI, Dual SPI, and Quad SPI. The Dual and Quad SPI controllers need a device specific startup script to get them into the right mode. This script should be fairly well explained by the comments. You should find at least one of these controllers that works for you. More recent versions of the controller have a Wishbone arbiter within them -- they're just not checked in the repo yet. (DSPI, QSPI). This makes it so the design fully supports two two Wishbone ports: a config port by which you can send any value and the memory mapped read port. (You can't use both at the same time.)
What are some alternatives?
When comparing dbgbus and qspiflash you can also consider the following projects:
wb2axip - Bus bridges and other odds and ends
openarty - An Open Source configuration of the Arty platform
sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces
zbasic - A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
Rudi-RV32I - A rudimental RISCV CPU supporting RV32I instructions, in VHDL
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
arrowzip - A ZipCPU based demonstration of the MAX1000 FPGA board
fpga_quick_ram_update - Quickly update a bitstream with new RAM contents
vgasim - A Video display simulator
videozip - A ZipCPU SoC for the Nexys Video board supporting video functionality