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My personal solution to this problem has been to convert bus commands to UART commands. In my world, however, the PC/host sets up the UART commands and the FPGA decodes them into bus commands and then encodes a return value. This is useful because it can be done in 2 wires. I've also done it for JTAG (similar to SPI as implemented) where it takes 4 wires. Check out my articles on the "debugging bus" if you'd like to read more about this approach. (I now have AXI drivers for my debugging bus as well.)
You might find quickly that it is difficult to get enough I/O's to do what you are asking for. (Two address channels, two data channels, byte strobes, two return channels and a whole lot of valid/ready signals.) An alternative protocol you might wish to look into would be Wishbone. Wishbone bus cycles are either read or write cycles--never both like AXI. When using Wishbone, the master creates a WE (write enable) signal which could be used to control the bus direction. You'd then drop one address channel (since Wishbone shares read/write addresses together), a couple bits of address (since Wishbone addresses are word addresses, not byte addresses), and multiplex the data channel. An AXI to Wishbone or even a Wishbone to AXI bridge might be valuable here.
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Testing Axi Slaves in Simulation
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Guys can u send me some github repositories on some simple project on system verilog with functionality like with couple functions ? Its my first reddit post in my life.
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A simple AXI-Lite register file
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AXI-Lite register bank revisited
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Connecting custom IP to microblaze