nybbleForth Alternatives

Similar projects and alternatives to nybbleForth

neorv32

77 1,415 9.9 C nybbleForth VS neorv32

:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
wb2axip

51 431 3.1 Verilog nybbleForth VS wb2axip

Bus bridges and other odds and ends
WorkOS

workos.com sponsored

The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
VexRiscv

21 2,244 7.6 Assembly nybbleForth VS VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation
Rudi-RV32I

7 106 0.0 VHDL nybbleForth VS Rudi-RV32I

A rudimental RISCV CPU supporting RV32I instructions, in VHDL
autofpga

9 156 4.3 C++ nybbleForth VS autofpga

A utility for Composing FPGA designs from Peripherals
sdspi

4 132 7.5 Verilog nybbleForth VS sdspi

SD-Card controller, using either SPI, SDIO, or eMMC interfaces
dbgbus

5 31 3.9 Verilog nybbleForth VS dbgbus

A collection of debugging busses developed and presented at zipcpu.com
InfluxDB

www.influxdata.com sponsored

Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better nybbleForth alternative or higher similarity.

Suggest an alternative to nybbleForth

nybbleForth reviews and mentions

Posts with mentions or reviews of nybbleForth. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-04-05.

CPU DESIGN
9 projects | /r/FPGA | 5 Apr 2021

Beware, however, that you'll get what you pay for. There are some very small 8b CPU's I've seen implemented in less than 1k LUTs (iCE40). (I think this was the one.) The 32b class I work with tends to require about 4k LUTs (iCE40), and while the CPU can often fit nicely in that space the rest any design using a CPU can get kind of tight. It will also cost you more to [pipeline your CPU](). The cache can be quite expensive as well, but still fits nicely within an Artix-7 35T class FPGA--depending on the size and implementation of your cache. There are also lower logic alternatives, but again ... with all of these there are performance tradeoffs. Again, you get what you pay for.

Stats

Basic nybbleForth repo stats

Mentions

Stars

Activity

0.0

Last Commit

over 6 years ago

The primary programming language of nybbleForth is Forth.

Popular Comparisons