Get non-trivial tests (and trivial, too!) suggested right inside your IDE, so you can code smart, create more value, and stay confident when you push. Learn more →
Similar projects and alternatives to lion
RISC-V Formal Verification Framework
A FPGA friendly 32 bit RISC-V CPU implementation
Clean code begins in your IDE with SonarLint. Up your coding game and discover issues early. SonarLint is a free plugin that helps you find & fix bugs and security issues from the moment you start writing code. Install from your favorite IDE marketplace today.
WIT (Wikipedia-based Image Text) Dataset is a large multimodal multilingual dataset comprising 37M+ image-text sets with 11M+ unique images across 100+ languages. (by google-research-datasets)
Prometheus Client Library for Modern C++
Project moved to: https://github.com/llvm/llvm-project
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Web-Scale Blockchain for fast, secure, scalable, decentralized apps and marketplaces.
TestGPT | Generating meaningful tests for busy devs. Get non-trivial tests (and trivial, too!) suggested right inside your IDE, so you can code smart, create more value, and stay confident when you push.
Understanding how atomics and memory ordering work
Abseil Common Libraries (C++)
Haskell to VHDL/Verilog/SystemVerilog compiler
Semantics of Virtual Machine for IELE prototype blockchain
lion reviews and mentions
A year of RISC-V adventures: embracing chaos in your software journey [video]
2 projects | news.ycombinator.com | 28 Aug 2022
I've been starting to dabble with digital logic design via Clash (https://clash-lang.org/), and there is a very cool-looking RISC-V SoC project done in that tool that looks fairly serious: https://github.com/standardsemiconductor/lion.
C++ Concurrency Model on x86 for Dummies
5 projects | news.ycombinator.com | 21 Aug 2022
That’s fascinating about the M1. In retrospect it seems like kind of a no-brainer but I doubt I would have thought of it.
SPARC had different memory models at different ISA revs IIRC: it’s been like 20 years since I was dealing with SPARC so I might be misremembering the details. Alpha would have been a better example.
RISC-V is really interesting. I’ve been slowly working through this: https://github.com/standardsemiconductor/lion, highly recommend!
Why More Networks Should Imitate Cardano When It Comes To Writing And Shipping Code | Bitcoinist.com
3 projects | reddit.com/r/CryptoCurrency | 6 Jun 2022
Interesting. Actually, you may be just the person to answer my question: Is it possible/plausible to run a Cardano node on Lion OS on a RISC-V machine? IMO, it would be great for the community if we could run all Cardano stake pools on end to end formally verified machines using open source core and hardware.
Hacker News top posts: Mar 4, 2021
3 projects | reddit.com/r/hackerdigest | 4 Mar 2021
Lion: A formally verified, 5-stage pipeline RISC-V core\ (30 comments)
Lion: A formally verified, 5-stage pipeline RISC-V core
2 projects | news.ycombinator.com | 4 Mar 2021
Where Lions Roam: RISC-V on the VELDT
4 projects | reddit.com/r/haskell | 28 Feb 2021
In addition, you can actually set the riscv-formal suite to verify correctness by k-induction: https://github.com/SymbioticEDA/riscv-formal/pull/28 https://symbiyosys.readthedocs.io/en/latest/quickstart.html#beyond-bounded-model-checks although I concur that by looking at https://github.com/standardsemiconductor/lion/blob/main/lion-formal/app/Main.hs the lion core is only verified with BMC.4 projects | reddit.com/r/haskell | 28 Feb 2021
Where Lions Roam: RISC-V on the VELDT
A note from our sponsor - CodiumAI
codium.ai | 30 May 2023
standardsemiconductor/lion is an open source project licensed under BSD 3-clause "New" or "Revised" License which is an OSI approved license.
The primary programming language of lion is Haskell.