RISC-V simulator

• toolchain

  4 - -

I am developing the risc-v simulator (https://gitlab.com/quantr/toolchain/riscv-simulator), we record every instructions+registers that qemu execute and compare them to ours. Is there any other way to cross-check the correctness of the execution of our simulator?

• riscv-isa-sim

  15 2,191 9.0 C

  Spike, a RISC-V ISA Simulator

  

Someone correct me if I'm wrong, but Spike is considered the gold standard for RISV-V simulation, in terms of support for extensions and overall correctness. As I understand it, QEMU is faster and easier to use for day-to-day for general software development.

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• riscv-formal

  10 550 0.0 Verilog

  RISC-V Formal Verification Framework

  

You might be able to hook up your simulator to risc v-formal https://github.com/SymbioticEDA/riscv-formal

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