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Riscv-isa-sim Alternatives
Similar projects and alternatives to riscv-isa-sim
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neorv32
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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buildroot
Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at https://gitlab.com/buildroot.org/buildroot/. Do not open issues or file pull requests here.
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ch32v307
Including the SDK、HDK、Datasheet of RISC-V MCU CH32V307 and other relevant development materials
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NOTE:
The number of mentions on this list indicates mentions on common posts plus user suggested alternatives.
Hence, a higher number means a better riscv-isa-sim alternative or higher similarity.
riscv-isa-sim discussion
riscv-isa-sim reviews and mentions
Posts with mentions or reviews of riscv-isa-sim.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-12-10.
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RISC-V simulator
Someone correct me if I'm wrong, but Spike is considered the gold standard for RISV-V simulation, in terms of support for extensions and overall correctness. As I understand it, QEMU is faster and easier to use for day-to-day for general software development.
- Help needed in building cavatools
- GCC 13 Adds RISC-V T-Head Vendor Extension Collection
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Hardware/software to run RISC-V ASM?
Spike is an RISC-V instruction set simulator: https://github.com/riscv-software-src/riscv-isa-sim
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most underrated cpp project you’ve seen?
I really like the source code for the Spike RISC-V ISA Simulator. It's not very heavily commented, though, so you really need to read the code.
- C++17 RISC-V RV32/64/128 userspace emulator library
- Buying RISC-V development board
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Is there a way to run RISCV sim spike on bare metal?
If you want to run bare metal with no RTOS, it should be possible, but you will need to replace the main startup program (https://github.com/riscv-software-src/riscv-isa-sim/blob/master/spike_main/spike.cc) with some program to set up the hardware and instantiate the simulator, load the OS image etc and then have a decent runtime environment to that supports malloc() etc and redirect IO to serial or flash memory etc. There is a bit of work you would need to do.
- switching between privilege levels
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Starting up with RISC-V
I guess you will also use Spike and the Sail model for RISC-V.
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Stats
Basic riscv-isa-sim repo stats
15
2,465
9.4
9 days ago
riscv-software-src/riscv-isa-sim is an open source project licensed under GNU General Public License v3.0 or later which is an OSI approved license.
The primary programming language of riscv-isa-sim is C.
Popular Comparisons
- riscv-isa-sim VS riscv-arch-test
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- riscv-isa-sim VS nanoCH32V305
- riscv-isa-sim VS riscv-none-elf-gcc-xpack
- riscv-isa-sim VS jailhouse
- riscv-isa-sim VS tinyemu
- riscv-isa-sim VS riscv-gnu-toolchain
- riscv-isa-sim VS discreture
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