riscv-isa-sim

Spike, a RISC-V ISA Simulator (by riscv-software-src)

Riscv-isa-sim Alternatives

Similar projects and alternatives to riscv-isa-sim

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better riscv-isa-sim alternative or higher similarity.

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Reviews and mentions

Posts with mentions or reviews of riscv-isa-sim. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-07-22.
  • Spike crashing after adding new instruction!!
    reddit.com/r/RISCV | 2021-08-24
    Why would spike not continue to decode addi to the pre-existing addi instruction in insns/addi.h? I'm pretty sure it fetches bytes, and uses the encoding MASKs to decide which instruction to dispatch to (see https://github.com/riscv/riscv-isa-sim/blob/master/riscv/encoding.h).
  • Porting an AVX-512 neural net C99 code generator to RISC-V
    reddit.com/r/RISCV | 2021-07-22

Stats

Basic riscv-isa-sim repo stats
2
1,145
9.6
7 days ago

riscv-software-src/riscv-isa-sim is an open source project licensed under GNU General Public License v3.0 or later which is an OSI approved license.

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