riscv-isa-sim
Spike, a RISC-V ISA Simulator (by riscv-software-src)
toolchain
By quantr
| riscv-isa-sim | toolchain | |
|---|---|---|
| 15 | 4 | |
| 2,211 | - | |
| 2.7% | - | |
| 9.0 | - | |
| 5 days ago | - | |
| C | ||
| GNU General Public License v3.0 or later | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-isa-sim
Posts with mentions or reviews of riscv-isa-sim.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-12-10.
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RISC-V simulator
Someone correct me if I'm wrong, but Spike is considered the gold standard for RISV-V simulation, in terms of support for extensions and overall correctness. As I understand it, QEMU is faster and easier to use for day-to-day for general software development.
- Help needed in building cavatools
- GCC 13 Adds RISC-V T-Head Vendor Extension Collection
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Hardware/software to run RISC-V ASM?
Spike is an RISC-V instruction set simulator: https://github.com/riscv-software-src/riscv-isa-sim
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most underrated cpp project you’ve seen?
I really like the source code for the Spike RISC-V ISA Simulator. It's not very heavily commented, though, so you really need to read the code.
- C++17 RISC-V RV32/64/128 userspace emulator library
- Buying RISC-V development board
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Is there a way to run RISCV sim spike on bare metal?
If you want to run bare metal with no RTOS, it should be possible, but you will need to replace the main startup program (https://github.com/riscv-software-src/riscv-isa-sim/blob/master/spike_main/spike.cc) with some program to set up the hardware and instantiate the simulator, load the OS image etc and then have a decent runtime environment to that supports malloc() etc and redirect IO to serial or flash memory etc. There is a bit of work you would need to do.
- switching between privilege levels
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Starting up with RISC-V
I guess you will also use Spike and the Sail model for RISC-V.
toolchain
Posts with mentions or reviews of toolchain.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-12-10.
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RISC-V simulator
I am developing the risc-v simulator (https://gitlab.com/quantr/toolchain/riscv-simulator), we record every instructions+registers that qemu execute and compare them to ours. Is there any other way to cross-check the correctness of the execution of our simulator?
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unable to register my debugger
Hi. my file META-INF/org.netbeans.api.debugger.LazyDebuggerManagerListener unable to register my debugger, my DebuggerManagerAdapter don't run, any hints? https://gitlab.com/quantr/toolchain/netbeans-riscv thanks Peter
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How to make this risc-v debugger/simulator UI more beautiful
buddy, all in here https://gitlab.com/quantr/toolchain. we are www.quantr.foundation
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riscv dev
here is repo https://gitlab.com/quantr/toolchain/riscv-simulator
What are some alternatives?
When comparing riscv-isa-sim and toolchain you can also consider the following projects:
sail-riscv - Sail RISC-V model
riscv-arch-test
rvv-intrinsic-doc
nanoCH32V305
riscv-gnu-toolchain - GNU toolchain for RISC-V, including GCC
qemu
jailhouse - Linux-based partitioning hypervisor
riscv-none-elf-gcc-xpack - A binary distribution of the GNU RISC-V Embedded GCC toolchain
discreture - A modern C++ library for efficiently and easily iterating through common combinatorial objects, such as combinations, permutations, partitions and more.
tinyemu - Fabrice Bellard's tinyemu (https://bellard.org/tinyemu/)
ch32v307 - Including the SDK、HDK、Datasheet of RISC-V MCU CH32V307 and other relevant development materials
riscv-opcodes - RISC-V Opcodes
riscv-isa-sim vs sail-riscv
riscv-isa-sim vs riscv-arch-test
riscv-isa-sim vs rvv-intrinsic-doc
riscv-isa-sim vs nanoCH32V305
riscv-isa-sim vs riscv-gnu-toolchain
riscv-isa-sim vs qemu
riscv-isa-sim vs jailhouse
riscv-isa-sim vs riscv-none-elf-gcc-xpack
riscv-isa-sim vs discreture
riscv-isa-sim vs tinyemu
riscv-isa-sim vs ch32v307
riscv-isa-sim vs riscv-opcodes