riscv-isa-sim
qemu
| riscv-isa-sim | qemu | |
|---|---|---|
| 15 | 37 | |
| 2,191 | - | |
| 1.8% | - | |
| 9.0 | - | |
| 5 days ago | - | |
| C | ||
| GNU General Public License v3.0 or later | - |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-isa-sim
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RISC-V simulator
Someone correct me if I'm wrong, but Spike is considered the gold standard for RISV-V simulation, in terms of support for extensions and overall correctness. As I understand it, QEMU is faster and easier to use for day-to-day for general software development.
- Help needed in building cavatools
- GCC 13 Adds RISC-V T-Head Vendor Extension Collection
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Hardware/software to run RISC-V ASM?
Spike is an RISC-V instruction set simulator: https://github.com/riscv-software-src/riscv-isa-sim
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most underrated cpp project you’ve seen?
I really like the source code for the Spike RISC-V ISA Simulator. It's not very heavily commented, though, so you really need to read the code.
- C++17 RISC-V RV32/64/128 userspace emulator library
- Buying RISC-V development board
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Is there a way to run RISCV sim spike on bare metal?
If you want to run bare metal with no RTOS, it should be possible, but you will need to replace the main startup program (https://github.com/riscv-software-src/riscv-isa-sim/blob/master/spike_main/spike.cc) with some program to set up the hardware and instantiate the simulator, load the OS image etc and then have a decent runtime environment to that supports malloc() etc and redirect IO to serial or flash memory etc. There is a bit of work you would need to do.
- switching between privilege levels
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Starting up with RISC-V
I guess you will also use Spike and the Sail model for RISC-V.
qemu
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QEMU AioContext removal and how it was done
https://gitlab.com/qemu-project/qemu/-/blob/master/hw/scsi/s...
QEMU's IOThreads allow the user to configure the threads and get something similar to thread per core architecture. But if 1 thread becomes a bottleneck, then some form of thread synchronization is needed again even with thread per core architecture. Some problems can be parallelized and they work well with thread per core.
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Why are Apple Silicon VMs so different?
Add `ENV ERL_FLAGS="+JPperf true"` to your Dockerfile and it will build just fine cross platform. The flag just changes some things during build time and won’t affect runtime performance.
[1] https://gitlab.com/qemu-project/qemu/-/issues/1034
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RISC-V Vector benchmark results
> I don't know how rdcycle works on qemu.
That's a good question! I had to look it up myself ...
Obviously qemu TCG isn't a cycle-accurate emulation. Using RDCYCLE / reading the corresponding CSR eventually calls https://gitlab.com/qemu-project/qemu/-/blob/69680740eafa1838... which calls cpu_get_host_ticks is basically an arch-independent wrapper around RDTSC.
So it just measures the time taken to run using RDTSC. Which I guess is what you would want (maybe?). It would measure the time taken to emulate the vector instruction in host instructions.
> This benchmark is more meant for developers to figure out how to vectorize algorithms effectively, as in which instructions to choose.
Absolutely, I'm not saying the qemu results would say anything very deep, but they're kind of interesting from the point of view of either optimizing qemu or if you have to use qemu because the hardware you want isn't available / isn't cheap enough.
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The IMPOSSIBLE RISCV HACK: Vector Extension 0.7.1-draft w/ current Linux kernel! – René Rebe
I see the commits that started switch support from RVV 071 to 100 start here, https://gitlab.com/qemu-project/qemu/-/commit/9ec6622db30df1c00d863c1ffc33341f9e0a534d
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I booted Linux 292,612 times
>> https://gitlab.com/qemu-project/qemu/-/issues/1696 ]
> Can I please just get the detail in mail instead of having to go look at random websites?
Maybe it's me but if I did boot boot linux 292.612 times to find a bug, you might as well click a link to a repository of a major open source project on a major git hosting service.
Is it really that weird to ask people online to check a website? Maybe I don't know the etiquette of these mail lists so this is a geniune question.
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Rise: Accelerate the Development of Open Source Software for RISC-V
Capstone is used[1] by QEMU as disassembly engine in debug logs and in monitor mode debugger, by the way, so it's in the scope of the RISE effort.
[1] https://gitlab.com/qemu-project/qemu/-/blob/master/disas/cap...
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Intel Arc 750 Crashes Host + Display Cable Workaround not needed anymore (Windows)
A user on the qemu bugtracker found a way to get the Intel Arc working across resets without crashing the host: Just don't passthrough the audio device of the GPU and everything works!
- Qemu 7.2.2: command line syntax in libvirt domain changed
- Anyone know if there's a way to disable ReBar on only one GPU?
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[RFT] Allow QEMU to expose static REBAR capability
[1]https://gitlab.com/qemu-project/qemu/-/commit/3412d8ec9810b819f8b79e8e0c6b87217c876e32 [2]https://gitlab.com/alex.williamson/qemu/-/commit/9a6d1822a2bd55f5dee1aec1b6529ae57949d5ba.patch
What are some alternatives?
riscv-arch-test
gcc
sail-riscv - Sail RISC-V model
riscv-binutils-gdb - RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
rvv-intrinsic-doc
nbdkit
nanoCH32V305
safeclib - safec libc extension with all C11 Annex K functions
riscv-gnu-toolchain - GNU toolchain for RISC-V, including GCC
lzbench - lzbench is an in-memory benchmark of open-source LZ77/LZSS/LZMA compressors
jailhouse - Linux-based partitioning hypervisor
CLK - A latency-hating emulator of: the Acorn Electron and Archimedes, Amstrad CPC, Apple II/II+/IIe and early Macintosh, Atari 2600 and ST, ColecoVision, Enterprise 64/128, Commodore Vic-20 and Amiga, MSX 1/2, Oric 1/Atmos, early PC compatibles, Sega Master System, Sinclair ZX80/81 and ZX Spectrum.