riscv-isa-sim
Spike, a RISC-V ISA Simulator (by riscv-software-src)
rvv-intrinsic-doc
By riscv-non-isa
| riscv-isa-sim | rvv-intrinsic-doc | |
|---|---|---|
| 15 | 6 | |
| 2,475 | 300 | |
| 2.7% | 2.7% | |
| 9.4 | 9.1 | |
| 7 days ago | 19 days ago | |
| C | C | |
| GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-isa-sim
Posts with mentions or reviews of riscv-isa-sim.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-12-10.
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RISC-V simulator
Someone correct me if I'm wrong, but Spike is considered the gold standard for RISV-V simulation, in terms of support for extensions and overall correctness. As I understand it, QEMU is faster and easier to use for day-to-day for general software development.
- Help needed in building cavatools
- GCC 13 Adds RISC-V T-Head Vendor Extension Collection
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Hardware/software to run RISC-V ASM?
Spike is an RISC-V instruction set simulator: https://github.com/riscv-software-src/riscv-isa-sim
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most underrated cpp project you’ve seen?
I really like the source code for the Spike RISC-V ISA Simulator. It's not very heavily commented, though, so you really need to read the code.
- C++17 RISC-V RV32/64/128 userspace emulator library
- Buying RISC-V development board
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Is there a way to run RISCV sim spike on bare metal?
If you want to run bare metal with no RTOS, it should be possible, but you will need to replace the main startup program (https://github.com/riscv-software-src/riscv-isa-sim/blob/master/spike_main/spike.cc) with some program to set up the hardware and instantiate the simulator, load the OS image etc and then have a decent runtime environment to that supports malloc() etc and redirect IO to serial or flash memory etc. There is a bit of work you would need to do.
- switching between privilege levels
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Starting up with RISC-V
I guess you will also use Spike and the Sail model for RISC-V.
rvv-intrinsic-doc
Posts with mentions or reviews of rvv-intrinsic-doc.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-09-12.
- Fixed length attributes · Issue #176 · riscv-non-isa/rvv-intrinsic-doc
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GCC 13.1 is now out... adds RVV vector intrinsics
Support for vector intrinsics as specified in version 0.11 of the RISC-V vector intrinsic specification, thanks Ju-Zhe Zhong from RiVAI for contributing most of implementation.
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RVV 1.0 assembly language example
The docs at https://github.com/riscv-non-isa/rvv-intrinsic-doc makes me think there should be a vfmacc_vv_f32m1_ta. I'll raise an issue there if it really is missing and not just me misunderstanding / using outdated stuff.
- Compiler Explorer supports RISC-V Clang with vector intrinsics
- Porting an AVX-512 neural net C99 code generator to RISC-V
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SQL on RISC-V Chip in Rust
If you're doing physics modeling or calculating light refractions or other stuff where you, a highly trained professional, have profiled and know that you'd benefit from V and the optimizer just isn't doing it, you can meet in the middle. The Vector Intrinsics are the contract between that highly trained professional and the compiler that aren't quite programming in assembly and handle the absurd avalanche (made easy by templates, but hard by C) of a templated/body that the optimizer can then easily inline without calling overhead and without blowing register allocation. It handles things like the generation of the 176 ways to find a maximum integer in an array. This is kind of the compromise between the autovectorization code not being able to decompose your nested Fortran loops or lighting effect in graphics or whatever but not quite reaching despair and coding it in assembly yourself. If you've ever programmed MMX, this will all look familiar.
What are some alternatives?
When comparing riscv-isa-sim and rvv-intrinsic-doc you can also consider the following projects:
riscv-arch-test
rvv_example - Simple demonstration of using the RISC-V Vector extension
sail-riscv - Sail RISC-V model
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
qemu
nanoCH32V305
riscv-none-elf-gcc-xpack - A binary distribution of the GNU RISC-V Embedded GCC toolchain
jailhouse - Linux-based partitioning hypervisor
riscv-gnu-toolchain - GNU toolchain for RISC-V, including GCC
tinyemu - Fabrice Bellard's tinyemu (https://bellard.org/tinyemu/)
discreture - A modern C++ library for efficiently and easily iterating through common combinatorial objects, such as combinations, permutations, partitions and more.
riscv-opcodes - RISC-V Opcodes
riscv-isa-sim vs riscv-arch-test
rvv-intrinsic-doc vs rvv_example
riscv-isa-sim vs sail-riscv
rvv-intrinsic-doc vs riscv-v-spec
riscv-isa-sim vs qemu
riscv-isa-sim vs nanoCH32V305
riscv-isa-sim vs riscv-none-elf-gcc-xpack
riscv-isa-sim vs jailhouse
riscv-isa-sim vs riscv-gnu-toolchain
riscv-isa-sim vs tinyemu
riscv-isa-sim vs discreture
riscv-isa-sim vs riscv-opcodes