riscv-isa-sim
Spike, a RISC-V ISA Simulator (by riscv-software-src)
riscv-arch-test
By riscv-non-isa
| riscv-isa-sim | riscv-arch-test | |
|---|---|---|
| 15 | 8 | |
| 2,475 | 523 | |
| 2.7% | 2.1% | |
| 9.4 | 8.8 | |
| 7 days ago | 26 days ago | |
| C | Assembly | |
| GNU General Public License v3.0 or later | Apache License 2.0 |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-isa-sim
Posts with mentions or reviews of riscv-isa-sim.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-12-10.
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RISC-V simulator
Someone correct me if I'm wrong, but Spike is considered the gold standard for RISV-V simulation, in terms of support for extensions and overall correctness. As I understand it, QEMU is faster and easier to use for day-to-day for general software development.
- Help needed in building cavatools
- GCC 13 Adds RISC-V T-Head Vendor Extension Collection
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Hardware/software to run RISC-V ASM?
Spike is an RISC-V instruction set simulator: https://github.com/riscv-software-src/riscv-isa-sim
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most underrated cpp project you’ve seen?
I really like the source code for the Spike RISC-V ISA Simulator. It's not very heavily commented, though, so you really need to read the code.
- C++17 RISC-V RV32/64/128 userspace emulator library
- Buying RISC-V development board
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Is there a way to run RISCV sim spike on bare metal?
If you want to run bare metal with no RTOS, it should be possible, but you will need to replace the main startup program (https://github.com/riscv-software-src/riscv-isa-sim/blob/master/spike_main/spike.cc) with some program to set up the hardware and instantiate the simulator, load the OS image etc and then have a decent runtime environment to that supports malloc() etc and redirect IO to serial or flash memory etc. There is a bit of work you would need to do.
- switching between privilege levels
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Starting up with RISC-V
I guess you will also use Spike and the Sail model for RISC-V.
riscv-arch-test
Posts with mentions or reviews of riscv-arch-test.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-10-20.
- Starting my Final Year Project on Architectural Validation of a RISC-V Core
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Heed help with riscv-arch-test
git: https://github.com/riscv-non-isa/riscv-arch-test.git commit: 6d87f30 (current master)
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Available (official) test suite?
There's also https://github.com/riscv-non-isa/riscv-arch-test, which I think is using similar tests to riscof (some generated by riscv_ctg) just an older framework to run it all.
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Problems with riscv-arch-test
Prior notice, I work for a professor and he wants me to test/verify a riscv simulation model, which is programmed in VHDL. He referred to the https://github.com/riscv-non-isa/riscv-arch-test , to look up how I have to set up a test.
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Compliance tests official repository
This is the current compliance test repository. https://github.com/riscv-non-isa/riscv-arch-test
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I’m working on a Rust library to help learners of RISC-V, thought you folks may find it interesting!
Have you tried running the RISC-V architectural test suite: https://github.com/riscv/riscv-arch-test? It should fit pretty nicely with your test system, each test generates a signature that needs to be checked against an expected output.
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FPGA and Simulation tools for Risc-V design
There are official RISC V tests you can run: https://github.com/riscv/riscv-compliance
What are some alternatives?
When comparing riscv-isa-sim and riscv-arch-test you can also consider the following projects:
sail-riscv - Sail RISC-V model
riscv-tests
rvv-intrinsic-doc
riscv-formal - RISC-V Formal Verification Framework
qemu
rrs - Rust RISC-V Simulator
nanoCH32V305
neorv32 - :desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
riscv-none-elf-gcc-xpack - A binary distribution of the GNU RISC-V Embedded GCC toolchain
openarty - An Open Source configuration of the Arty platform
jailhouse - Linux-based partitioning hypervisor
riscof
riscv-isa-sim vs sail-riscv
riscv-arch-test vs riscv-tests
riscv-isa-sim vs rvv-intrinsic-doc
riscv-arch-test vs riscv-formal
riscv-isa-sim vs qemu
riscv-arch-test vs rrs
riscv-isa-sim vs nanoCH32V305
riscv-arch-test vs neorv32
riscv-isa-sim vs riscv-none-elf-gcc-xpack
riscv-arch-test vs openarty
riscv-isa-sim vs jailhouse
riscv-arch-test vs riscof