riscv-isa-sim VS jailhouse

Someone correct me if I'm wrong, but Spike is considered the gold standard for RISV-V simulation, in terms of support for extensions and overall correctness. As I understand it, QEMU is faster and easier to use for day-to-day for general software development.

Spike is an RISC-V instruction set simulator: https://github.com/riscv-software-src/riscv-isa-sim

I really like the source code for the Spike RISC-V ISA Simulator. It's not very heavily commented, though, so you really need to read the code.

If you want to run bare metal with no RTOS, it should be possible, but you will need to replace the main startup program (https://github.com/riscv-software-src/riscv-isa-sim/blob/master/spike_main/spike.cc) with some program to set up the hardware and instantiate the simulator, load the OS image etc and then have a decent runtime environment to that supports malloc() etc and redirect IO to serial or flash memory etc. There is a bit of work you would need to do.

I guess you will also use Spike and the Sail model for RISC-V.

You could run it inside something like jailhouse hypervisor (https://github.com/siemens/jailhouse) if you want to give it direct dedicated "baremetal" access to hardware. You could do this inside of a buildroot linux image. This would need a customized simulator.

Yes indeed, and Siemens even has their own hypervisor: https://github.com/siemens/jailhouse

Yeah, I think that is what something like https://www.toradex.com/computer-on-modules/apalis-arm-family/nxp-imx-8 is useful for, where it has a separate core. Or even on linux you can use isolcpus to get pseudo-isolation. There are also hardware hypervisors like Jailhouse (https://github.com/siemens/jailhouse) which can completely isolate hardware resources and I suppose might prevent the GPU from causing an issue with realtime task. But this definitely affects ease-of-use and probably requires a reduced feature set in the language (no dynamic allocations) and lots of unsafe code.