riscv-isa-sim
Spike, a RISC-V ISA Simulator (by riscv-software-src)
riscv-none-elf-gcc-xpack
A binary distribution of the GNU RISC-V Embedded GCC toolchain (by xpack-dev-tools)
| riscv-isa-sim | riscv-none-elf-gcc-xpack | |
|---|---|---|
| 15 | 2 | |
| 2,624 | 154 | |
| 2.9% | 5.3% | |
| 9.3 | 9.3 | |
| 7 days ago | 3 days ago | |
| C | C++ | |
| GNU General Public License v3.0 or later | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-isa-sim
Posts with mentions or reviews of riscv-isa-sim.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-12-10.
-
RISC-V simulator
Someone correct me if I'm wrong, but Spike is considered the gold standard for RISV-V simulation, in terms of support for extensions and overall correctness. As I understand it, QEMU is faster and easier to use for day-to-day for general software development.
- Help needed in building cavatools
- GCC 13 Adds RISC-V T-Head Vendor Extension Collection
-
Hardware/software to run RISC-V ASM?
Spike is an RISC-V instruction set simulator: https://github.com/riscv-software-src/riscv-isa-sim
-
most underrated cpp project you’ve seen?
I really like the source code for the Spike RISC-V ISA Simulator. It's not very heavily commented, though, so you really need to read the code.
- C++17 RISC-V RV32/64/128 userspace emulator library
- Buying RISC-V development board
-
Is there a way to run RISCV sim spike on bare metal?
If you want to run bare metal with no RTOS, it should be possible, but you will need to replace the main startup program (https://github.com/riscv-software-src/riscv-isa-sim/blob/master/spike_main/spike.cc) with some program to set up the hardware and instantiate the simulator, load the OS image etc and then have a decent runtime environment to that supports malloc() etc and redirect IO to serial or flash memory etc. There is a bit of work you would need to do.
- switching between privilege levels
-
Starting up with RISC-V
I guess you will also use Spike and the Sail model for RISC-V.
riscv-none-elf-gcc-xpack
Posts with mentions or reviews of riscv-none-elf-gcc-xpack.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-04-29.
-
RISC-V MCU development boards
most interesting here seems WCH CH32V20* according to their docs https://github.com/wuxx/nanoCH32V305#open-source-toolchain we can use the open source toolchain https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack to build and flash their chips, so no need to use their IDE.
-
GCC 13 Adds RISC-V T-Head Vendor Extension Collection
Yep, would be nice to get that one in, but have not seen anything beyond xpack discussion.
What are some alternatives?
When comparing riscv-isa-sim and riscv-none-elf-gcc-xpack you can also consider the following projects:
riscv-arch-test
riscv-gnu-toolchain - GNU toolchain for RISC-V, including GCC
qemu
ccache - ccache – a fast compiler cache
riscv-opcodes - RISC-V Opcodes
meson-build-xpack - A binary distribution of the meson build tool