riscv-isa-sim
ch32v307
riscv-isa-sim | ch32v307 | |
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15 | 8 | |
2,191 | 342 | |
3.7% | - | |
9.0 | 4.0 | |
5 days ago | about 2 months ago | |
C | C | |
GNU General Public License v3.0 or later | - |
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-isa-sim
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RISC-V simulator
Someone correct me if I'm wrong, but Spike is considered the gold standard for RISV-V simulation, in terms of support for extensions and overall correctness. As I understand it, QEMU is faster and easier to use for day-to-day for general software development.
- Help needed in building cavatools
- GCC 13 Adds RISC-V T-Head Vendor Extension Collection
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Hardware/software to run RISC-V ASM?
Spike is an RISC-V instruction set simulator: https://github.com/riscv-software-src/riscv-isa-sim
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most underrated cpp project you’ve seen?
I really like the source code for the Spike RISC-V ISA Simulator. It's not very heavily commented, though, so you really need to read the code.
- C++17 RISC-V RV32/64/128 userspace emulator library
- Buying RISC-V development board
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Is there a way to run RISCV sim spike on bare metal?
If you want to run bare metal with no RTOS, it should be possible, but you will need to replace the main startup program (https://github.com/riscv-software-src/riscv-isa-sim/blob/master/spike_main/spike.cc) with some program to set up the hardware and instantiate the simulator, load the OS image etc and then have a decent runtime environment to that supports malloc() etc and redirect IO to serial or flash memory etc. There is a bit of work you would need to do.
- switching between privilege levels
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Starting up with RISC-V
I guess you will also use Spike and the Sail model for RISC-V.
ch32v307
- My alpha Pico-based CH32V003 debug tool is ready for a few testers
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Hardware/software to run RISC-V ASM?
VCC-GND Studio is about to launch similar boards based on CH32V307.
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EPS32 but for wired Ethernet instead?
But if you're looking for RISC-V + integrated PHY, take a look at WCH's CH32V307 - just add magnetics, termination and an RJ45 jack and you've got 10BaseT.
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MCU dev board with 5 UARTs?
Yes, English datasheets can be found - along with code examples, board schematics etc - at the openwch/ch32v307 Github repo.
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Useful Tools and Resources for RISC-V development
More realistically, I DO think there's value for a terminal server that's just an ethernet connection (even one that's ancient) with some amount of programmability that's connected to 80 GPIO pins, some of which may be serial ports. I could imagine testing 1-2 Raspberry Pi-class with a bed of nails style test jig that confirms that all the GPIO, JTAG, and such are at least toggleable by sending synchronized signals to the BeagleBone/VisionFive/ESP32-C3/ whatever to confirm that all the I/O pins survived the fine wires from the wafer to the package plus all intervening PCB vias and soldering and so on. (Maybe you can't test board X with another board X because there's a different number of inputs and outputs.)
- The RISC-V MCU CH32V307 is a bad boy
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New $10 Risc-V development board
looks to be IMAFC from the PDF on their github (https://github.com/openwch/ch32v307/blob/main/Datasheet/CH32V20x_30xDS0.PDF)
What are some alternatives?
riscv-arch-test
pico-examples
sail-riscv - Sail RISC-V model
ch32-rs - Embedded Rust device crates for WCH's RISC-V and Cortex-M microcontrollers
rvv-intrinsic-doc
Energia - Fork of Arduino for the Texas Instruments LaunchPad's
nanoCH32V305
freedom-tools - Tools for SiFive's Freedom Platform
riscv-gnu-toolchain - GNU toolchain for RISC-V, including GCC
riscv-openocd-wch - This is the OpenOCD source code modified to support WCHlink and CH32Vxxx MCUs, received from MounRiver after my GPL request, and published here as a service for everyone interested, BTW: 8bitgeek is putting in a lot of effort to make it workable on Linux, check their fork! I claim no copyright on any of it, and I'm only exercising the rights granted by the GPL.
qemu
RISC-V-Guide - RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.