riscv-isa-sim
Spike, a RISC-V ISA Simulator (by riscv-software-src)
neorv32
:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. (by stnolting)
| riscv-isa-sim | neorv32 | |
|---|---|---|
| 15 | 77 | |
| 2,211 | 1,429 | |
| 2.7% | - | |
| 9.0 | 9.9 | |
| 6 days ago | 6 days ago | |
| C | C | |
| GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-isa-sim
Posts with mentions or reviews of riscv-isa-sim.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-12-10.
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RISC-V simulator
Someone correct me if I'm wrong, but Spike is considered the gold standard for RISV-V simulation, in terms of support for extensions and overall correctness. As I understand it, QEMU is faster and easier to use for day-to-day for general software development.
- Help needed in building cavatools
- GCC 13 Adds RISC-V T-Head Vendor Extension Collection
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Hardware/software to run RISC-V ASM?
Spike is an RISC-V instruction set simulator: https://github.com/riscv-software-src/riscv-isa-sim
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most underrated cpp project you’ve seen?
I really like the source code for the Spike RISC-V ISA Simulator. It's not very heavily commented, though, so you really need to read the code.
- C++17 RISC-V RV32/64/128 userspace emulator library
- Buying RISC-V development board
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Is there a way to run RISCV sim spike on bare metal?
If you want to run bare metal with no RTOS, it should be possible, but you will need to replace the main startup program (https://github.com/riscv-software-src/riscv-isa-sim/blob/master/spike_main/spike.cc) with some program to set up the hardware and instantiate the simulator, load the OS image etc and then have a decent runtime environment to that supports malloc() etc and redirect IO to serial or flash memory etc. There is a bit of work you would need to do.
- switching between privilege levels
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Starting up with RISC-V
I guess you will also use Spike and the Sail model for RISC-V.
neorv32
Posts with mentions or reviews of neorv32.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-03-08.
- An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
- NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL
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Recommendations for RISC-V on FPGA
How about NEORV32?
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
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RISCV CPU using PL on Pynq Z2 Development Board
NEORV32 is an open source soft core and very well documented. I would recommend you to take a look at it and play around a bit. And it is certainly possible to have a soft core running on only the PL side without PS interference.
- A tiny 1-Wire controller for FPGAs (in VHDL)
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Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
What are some alternatives?
When comparing riscv-isa-sim and neorv32 you can also consider the following projects:
sail-riscv - Sail RISC-V model
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
riscv-arch-test
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
rvv-intrinsic-doc
picoMIPS - picoMIPS processor doing affine transformation
nanoCH32V305
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
riscv-gnu-toolchain - GNU toolchain for RISC-V, including GCC
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
qemu
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
riscv-isa-sim vs sail-riscv
neorv32 vs VexRiscv
riscv-isa-sim vs riscv-arch-test
neorv32 vs linux-on-litex-vexriscv
riscv-isa-sim vs rvv-intrinsic-doc
neorv32 vs picoMIPS
riscv-isa-sim vs nanoCH32V305
neorv32 vs upduino-projects
riscv-isa-sim vs riscv-gnu-toolchain
neorv32 vs chipyard
riscv-isa-sim vs qemu
neorv32 vs lxp32-cpu