riscv-isa-sim
Spike, a RISC-V ISA Simulator (by riscv-software-src)
riscv-opcodes
RISC-V Opcodes (by riscv)
| riscv-isa-sim | riscv-opcodes | |
|---|---|---|
| 15 | 5 | |
| 2,211 | 612 | |
| 2.7% | 0.7% | |
| 9.0 | 7.7 | |
| 5 days ago | 3 days ago | |
| C | Python | |
| GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-isa-sim
Posts with mentions or reviews of riscv-isa-sim.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-12-10.
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RISC-V simulator
Someone correct me if I'm wrong, but Spike is considered the gold standard for RISV-V simulation, in terms of support for extensions and overall correctness. As I understand it, QEMU is faster and easier to use for day-to-day for general software development.
- Help needed in building cavatools
- GCC 13 Adds RISC-V T-Head Vendor Extension Collection
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Hardware/software to run RISC-V ASM?
Spike is an RISC-V instruction set simulator: https://github.com/riscv-software-src/riscv-isa-sim
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most underrated cpp project you’ve seen?
I really like the source code for the Spike RISC-V ISA Simulator. It's not very heavily commented, though, so you really need to read the code.
- C++17 RISC-V RV32/64/128 userspace emulator library
- Buying RISC-V development board
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Is there a way to run RISCV sim spike on bare metal?
If you want to run bare metal with no RTOS, it should be possible, but you will need to replace the main startup program (https://github.com/riscv-software-src/riscv-isa-sim/blob/master/spike_main/spike.cc) with some program to set up the hardware and instantiate the simulator, load the OS image etc and then have a decent runtime environment to that supports malloc() etc and redirect IO to serial or flash memory etc. There is a bit of work you would need to do.
- switching between privilege levels
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Starting up with RISC-V
I guess you will also use Spike and the Sail model for RISC-V.
riscv-opcodes
Posts with mentions or reviews of riscv-opcodes.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-04-28.
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How to improve the RISC-V specification
It uses machine-readable specs from https://github.com/riscv/riscv-opcodes ; yet I needed to extract immediate bit scrambling from their LaTeX sources :). I wonder if there is an easier way. Anyways, the opcode semantics are hand-coded and it simulates enough to boot linux.
- Help needed in building cavatools
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RISC-V remaining insn free space
A couple of hours work would allow someone to work it out exactly by parsing the files in https://github.com/riscv/riscv-opcodes. I don't know whether the existing parse.py explicitly works this out. It does check for conflicts. If it doesn't provide this information now then it should be easy to add.
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How to extend Risc-V P extension in riscv-gcc and riscv-binutils?
Add instruction's match and mask values and optionally add DECLARE_INSN definitions (include/opcode/riscv-opc.h). You can use riscv-opcodes to generate those mask/match values.
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Programming 101: writing a RISCV assembler - the worlds smallest!
I'm a bit surprised René doesn't know about either https://github.com/riscv/riscv-opcodes or https://github.com/michaeljclark/riscv-meta
What are some alternatives?
When comparing riscv-isa-sim and riscv-opcodes you can also consider the following projects:
sail-riscv - Sail RISC-V model
riscv-meta - RISC-V Instruction Set Metadata
riscv-arch-test
riscv-gcc
rvv-intrinsic-doc
binutils-gdb
nanoCH32V305
riscv-binutils-gdb - RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
riscv-gnu-toolchain - GNU toolchain for RISC-V, including GCC
cavatools - Cavatools is a RISC-V architectural simulator.
qemu
riscv-binutils-devmemo - binutils development memo (for RISC-V)
riscv-isa-sim vs sail-riscv
riscv-opcodes vs riscv-meta
riscv-isa-sim vs riscv-arch-test
riscv-opcodes vs riscv-gcc
riscv-isa-sim vs rvv-intrinsic-doc
riscv-opcodes vs binutils-gdb
riscv-isa-sim vs nanoCH32V305
riscv-opcodes vs riscv-binutils-gdb
riscv-isa-sim vs riscv-gnu-toolchain
riscv-opcodes vs cavatools
riscv-isa-sim vs qemu
riscv-opcodes vs riscv-binutils-devmemo