riscv-isa-sim VS rvv-intrinsic-doc

Someone correct me if I'm wrong, but Spike is considered the gold standard for RISV-V simulation, in terms of support for extensions and overall correctness. As I understand it, QEMU is faster and easier to use for day-to-day for general software development.

Spike is an RISC-V instruction set simulator: https://github.com/riscv-software-src/riscv-isa-sim

I really like the source code for the Spike RISC-V ISA Simulator. It's not very heavily commented, though, so you really need to read the code.

If you want to run bare metal with no RTOS, it should be possible, but you will need to replace the main startup program (https://github.com/riscv-software-src/riscv-isa-sim/blob/master/spike_main/spike.cc) with some program to set up the hardware and instantiate the simulator, load the OS image etc and then have a decent runtime environment to that supports malloc() etc and redirect IO to serial or flash memory etc. There is a bit of work you would need to do.

I guess you will also use Spike and the Sail model for RISC-V.

To figure out how the environment works, I built a spike model with https://github.com/riscv-software-src/riscv-isa-sim So I tried now to verify the spike model, but I always get the error: "Target simulator executable 'spike' not found." when I use the "make" command.

The docs at https://github.com/riscv-non-isa/rvv-intrinsic-doc makes me think there should be a vfmacc_vv_f32m1_ta. I'll raise an issue there if it really is missing and not just me misunderstanding / using outdated stuff.