riscv-formal
RISC-V Formal Verification Framework (by SymbioticEDA)
simple-riscv
A simple three-stage RISC-V CPU (by hamsternz)
| riscv-formal | simple-riscv | |
|---|---|---|
| 10 | 5 | |
| 550 | 19 | |
| 3.6% | - | |
| 0.0 | 2.7 | |
| about 2 years ago | about 3 years ago | |
| Verilog | VHDL | |
| ISC License | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-formal
Posts with mentions or reviews of riscv-formal.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-12-10.
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RISC-V simulator
You might be able to hook up your simulator to risc v-formal https://github.com/SymbioticEDA/riscv-formal
- how is to use symbiflow in my fpga projects.
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Machine readable specifications at scale
Then we have RISC, which wrote their own formal verification toolchain here. They just generate Verilog with a Python script. AFAICT this would be really hard to adapt to an assembler. Fortunately the ISA is simple to implement.
- Looking for an rv32i asm program that covers all possible scenarios of all instructions for testing
- Is a single cycle CPU of any use besides learning?
- When to use Formal Verification vs Simulation?
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Where Lions Roam: RISC-V on the VELDT
Your question is certainly not dumb; on the contrary, it is very important! I suppose the developers are responsible for verifying the formal verifier and ensuring it covers the spec. Maybe there is a way to formally verify the formal verifier? Either way, I must give a shout out to the riscv-formal project and its contributors; the project was instrumental to the development of Lion.
Not trying to put words in your mouth, but I do want to clarify something for this audience: the bound in the BMC done by the riscv-formal suite is on the number of cycles, not on the number of bits. Case in point, when you try to BMC the (M)ultiply extensions with the riscv-formal suite, you're actually not allowed to use multiplication because the state space blows up: https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md#alternative-arithmetic-operations
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Any advices for my first RISC-V Core in Verilog ?
Use riscv-formal. It will save a ton of headaches trying to track down a bad instruction. It can generate a module that does checks on the fly during normal sims.
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FPGA and Simulation tools for Risc-V design
I recommend SymbiYosys for formally testing your CPU before ever placing it into a simulation. You can use the riscv-formal property set to get you started, but I'd personally go for an inductive proof of some type and the riscv-formal property set may not get you that far.
simple-riscv
Posts with mentions or reviews of simple-riscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-11-23.
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How to run DOOM on a custom-made CPU in VHDL
Have a look at https://github.com/hamsternz/simple-riscv/tree/main/sw for how I did this for my toy processor. In particular https://github.com/hamsternz/simple-riscv/tree/main/sw/image_to_mem does the heavy lifting.
- Running VIVADO project from batch- linux , by using tcl file.
- Looking for an rv32i asm program that covers all possible scenarios of all instructions for testing
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Is a single cycle CPU of any use besides learning?
If you want to see my ISA testing source have a look at: https://github.com/hamsternz/simple-riscv/blob/main/sw/asm/isa_test.S
What are some alternatives?
When comparing riscv-formal and simple-riscv you can also consider the following projects:
riscv-arch-test
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
lion - Where Lions Roam: RISC-V on the VELDT
riscv-tests
rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
Cores-VeeR-EH1 - VeeR EH1 core
autofpga - A utility for Composing FPGA designs from Peripherals
openarty - An Open Source configuration of the Arty platform
hs-arm - (Dis)assembler and analyzer generated from the machine-readable ARMv8.3-A specification
riscv-formal vs riscv-arch-test
simple-riscv vs neo430
riscv-formal vs lion
simple-riscv vs riscv-tests
riscv-formal vs rp32
simple-riscv vs rp32
riscv-formal vs riscv-tests
simple-riscv vs Cores-VeeR-EH1
riscv-formal vs Cores-VeeR-EH1
riscv-formal vs autofpga
riscv-formal vs openarty
riscv-formal vs hs-arm