rp32
friscv
| rp32 | friscv | |
|---|---|---|
| 3 | 1 | |
| 8 | 15 | |
| - | - | |
| 5.9 | 7.7 | |
| 8 months ago | 14 days ago | |
| SystemVerilog | Coq | |
| Apache License 2.0 | MIT License |
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rp32
-
How to design a more elegant and simple instraction decoder
Here is my decoder: https://github.com/jeras/rp32/blob/master/hdl/rtl/riscv/riscv_isa_i_pkg.sv
- Mapping compressed 'C' instructions to their 32b counterparts.
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Is a single cycle CPU of any use besides learning?
I am writing a RISC-V core with a strict IPC=1 (instructions per cycle). One piece is still in my mind, but the CPU is already passing instruction set tests.https://github.com/jeras/rp32The code was not properly synthesized yet, and there is almost no documentation, if you wish to use anything, but do not know how to, you can ask for help as a GitHub issue. But I do not know how much time I will have to answer.
friscv
What are some alternatives?
riscv-formal - RISC-V Formal Verification Framework
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Cores-VeeR-EH1 - VeeR EH1 core
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
simple-riscv - A simple three-stage RISC-V CPU
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform