friscv
cheshire
| friscv | cheshire | |
|---|---|---|
| 1 | 1 | |
| 17 | 186 | |
| - | 10.2% | |
| 4.7 | 6.9 | |
| 3 days ago | 4 days ago | |
| SystemVerilog | Verilog | |
| MIT License | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
friscv
cheshire
-
Cpu project
If you want to see the difference in scale you may want to compare the Cheshire SoC (Linux capable) here
What are some alternatives?
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ApogeoRV - A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
libsv - An open source, parameterized SystemVerilog digital hardware IP library
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
pulpissimo - This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
fpga_riscv_cpu - fpga verilog risc-v rv32i cpu
Arithmetic-Circuits - This repository contains different modules which execute arithmetic operations.