friscv
cheshire
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| friscv | cheshire | |
|---|---|---|
| 1 | 1 | |
| 14 | 102 | |
| - | - | |
| 8.4 | 7.8 | |
| 2 months ago | 5 days ago | |
| Coq | SystemVerilog | |
| MIT License | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
friscv
cheshire
-
Cpu project
If you want to see the difference in scale you may want to compare the Cheshire SoC (Linux capable) here
What are some alternatives?
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pulpissimo - This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
libsv - An open source, parameterized SystemVerilog digital hardware IP library
Cores-VeeR-EH1 - VeeR EH1 core
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux