darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
XiangShan
Open-source high-performance RISC-V processor (by OpenXiangShan)
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| darkriscv | XiangShan | |
|---|---|---|
| 3 | 28 | |
| 1,630 | 3,633 | |
| 1.2% | 2.4% | |
| 2.8 | 9.5 | |
| 5 months ago | 4 days ago | |
| Verilog | Scala | |
| BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
darkriscv
Posts with mentions or reviews of darkriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-20.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
XiangShan
Posts with mentions or reviews of XiangShan.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-05-04.
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How to build a Startup use open source chips
If you are interested in high performance look into vroom , c910 and xianghan, maybe you could adopt one of them.
- Open-source high-performance RISC-V processor
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I see that many open riscv cores use Scala that generate verilog. Is this common practice?
Here’s a good example of one: https://github.com/OpenXiangShan/XiangShan
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How Much Would It Cost For A Truly Open Source RISC-V SOC?
There are already open source designs that are reportedly close to older ARM smartphone design in term of performance (c910 and xiangshang).
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RISC-V Pushes into the Mainstream
> Because at this point they have more to gain than by keeping them proprietary. RISC-V is not yet overall competitive with ARM. So it's not like these RISC-V cores could be commercialized that successfully. Keeping them open probably makes further development faster.
This open source core is about equivalent to a Cortex-X1. https://github.com/OpenXiangShan/XiangShan
- VisionFive 2 RISC-V single-board computer is up for pre-order for $56 and up
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I am bored because I am not capable to work and want to learn something useful/interesting
Then you can help open source hardware designs like xiangshan or vroom.
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server/workstation-grade HPC RISC-V microprocessors?
There is vroom , c910 iirc is used by alibaba for servers, xiangshan i think aims at ARM smartphone chromebook performance level (like the c910).
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RISC-V only takes 12 years to achieve the milestone of 10 billion cores, 5 years faster than ARM.
To me at least the fact that the ISA is royalty free means that open source cores can be developed (Some did that target high performance smartphone and server use cases).
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"Imagination launches IMG RTXM-2200 – its first real-time embedded RISC-V CPU"
Also would be hard competing with ARM A73 class open source riscv cores like XiangShan and the T-head which are out-of-order, superscalar, and multicore capable.
What are some alternatives?
When comparing darkriscv and XiangShan you can also consider the following projects:
biriscv - 32-bit Superscalar RISC-V CPU
openc910 - OpenXuantie - OpenC910 Core
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
peakperf - Achieve peak performance on x86 CPUs and NVIDIA GPUs
Cores-VeeR-EH1 - VeeR EH1 core
chisel - Chisel: A Modern Hardware Design Language
redroid-doc - redroid (Remote-Android) is a multi-arch, GPU enabled, Android in Cloud solution. Track issues / docs here
riscv - RISC-V CPU Core (RV32IM)
cpufetch - Simple yet fancy CPU architecture fetching tool
friscv - RISCV CPU implementation in SystemVerilog
learnxinyminutes-docs - Code documentation written as code! How novel and totally my idea!