darkriscv
XiangShan
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| darkriscv | XiangShan | |
|---|---|---|
| 3 | 32 | |
| 1,882 | 4,305 | |
| 2.8% | 2.4% | |
| 6.3 | 9.3 | |
| 8 days ago | 6 days ago | |
| Verilog | Scala | |
| BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 or later |
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
darkriscv
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
XiangShan
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Loongson 3A6000: A Star Among Chinese CPUs
Are you calling for the government to pick a winner? The Chinese word for this fierce if at times chaotic competition is "juan". It worked for them in EV and PV. The outcome remains to be seen in chips and commercial space launches. But even their mostly (ex-)students-run open source Xiangshan RiscV project https://github.com/OpenXiangShan/XiangShan shows a remarkable level of sophistication.
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MRISC32 – An Open 32-Bit RISC/Vector ISA (Suitable for FPGA CPU)
> Certainly no RISC-V implementations that are in the hands of customers right now do any fusion and it doesn't seem to hurt their ability to match or exceed the performance of similar Arm cores (A55, A72).
You can play around with OpenXianShan though, they have a few fusion targets: https://github.com/OpenXiangShan/XiangShan/blob/master/src/m...
Most of the targets require the same destination, so it won't be able to fuse current codegen. I suppose there is still some time before compilers need to be ready, but it's not that much.
> Perhaps they will provide compiler patches if required.
I hope so, btw t-head seems to be still be trying to upstream XTheadVector: https://gcc.gnu.org/pipermail/gcc-patches/2024-January/64278...
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Ask HN: Are there any open source dual-issue RISC-V processor
This is the most advanced open source risc-v implementation I'm awair of: https://github.com/OpenXiangShan/XiangShan
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How can I leverage RISC-V in my final year Electrical & Electronics Engineering project? Seeking advice and project ideas.
Maybe implement a big feature for a open source design? like vroom or xiangshan.
- 大炼芯运动彻底破产，跪舔韩国要技术
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New processor, OS to propel open-source chip ecosystem
I did know about XiangShan, but not Aolai. Is it a Linux distribution?
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How to build a Startup use open source chips
If you are interested in high performance look into vroom , c910 and xianghan, maybe you could adopt one of them.
- Open-source high-performance RISC-V processor
What are some alternatives?
biriscv - 32-bit Superscalar RISC-V CPU
openc910 - OpenXuantie - OpenC910 Core
riscv - RISC-V CPU Core (RV32IM)
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
peakperf - Achieve peak performance on x86 CPUs and NVIDIA GPUs
Cores-VeeR-EH1 - VeeR EH1 core
chisel - Chisel: A Modern Hardware Design Language
friscv - RISCV CPU implementation in SystemVerilog
redroid-doc - redroid (Remote-Android) is a multi-arch, GPU enabled, Android in Cloud solution. Track issues / docs here
meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture
cpufetch - Simple yet fancy CPU architecture fetching tool