Verilog rv32e

Open-source Verilog projects categorized as rv32e

Verilog rv32e Projects

  1. darkriscv

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

    Project mention: Opensouce RISC-V CPU core implemented in Verilog from scratch in one night | news.ycombinator.com | 2025-03-16
  2. InfluxDB

    InfluxDB – Built for High-Performance Time Series Workloads. InfluxDB 3 OSS is now GA. Transform, enrich, and act on time series data directly in the database. Automate critical tasks and eliminate the need to move data externally. Download now.

    InfluxDB logo
NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

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Verilog rv32e related posts

  • Opensouce RISC-V CPU core implemented in Verilog from scratch in one night

    1 project | news.ycombinator.com | 16 Mar 2025
  • As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?

    1 project | /r/FPGA | 9 Jan 2022

Index

# Project Stars
1 darkriscv 2,316

Sponsored
InfluxDB – Built for High-Performance Time Series Workloads
InfluxDB 3 OSS is now GA. Transform, enrich, and act on time series data directly in the database. Automate critical tasks and eliminate the need to move data externally. Download now.
www.influxdata.com

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