As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?

• darkriscv

  3 1,882 6.3 Verilog

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  

This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.

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