Verilog Riscv

Open-source Verilog projects categorized as Riscv
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Verilog Fpga risc-v Cpu Rv32i
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Top 9 Verilog Riscv Projects

Riscv

  1. darkriscv

    opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

    Project mention: Opensouce RISC-V CPU core implemented in Verilog from scratch in one night | news.ycombinator.com | 2025-03-16

  2. Stream

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  3. kianRiscV

    RISC-V Linux SoC, marchID: 0x2b

  4. Hazard3

    3-stage RV32IMACZb* processor with debug

    Project mention: ARMv9 Architecture Helps Lift Arm to New Financial Heights | news.ycombinator.com | 2025-05-18

    It is funny that you should say that, considering that I was wondering this myself earlier today WRT the Hazard3 cores in the RP2350. It turns out someone did benchmarks:

    https://icircuit.net/benchmarking-raspberry-pi-pico-2/3983

    The Hazard3 cores was designed by a single person while the ARM Cortex cores were presumably designed by a team of people. The hazard3 cores mostly run circles around the Cortex-M0+ cores in the older RP2040 and are competitive with the Cortex-M33 cores that share the RP2350 silicon. For integer addition and multiplication, they actually outperform the Cortex-M33 cores. The Hazard3 cores are open source:

    https://github.com/Wren6991/Hazard3

    That said, not all RISC-V designs are open source, but some of the open source ones are performance competitive with higher end closed source cores, such as the SonicBoom core from Berkeley:

    https://adept.eecs.berkeley.edu/wiki/_media/eop/adept-eop-je...

    As for the other problem you cite, the RP2350 has both RISC-V and ARM cores. It is a certainty that if the ARM cores had not been present, the RP2350 would have been cheaper, since less die area would have been needed and ARM license fees would have been avoided.

  5. riscv_vhdl

    Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

  6. cheshire

    A minimal Linux-capable 64-bit RISC-V SoC built around CVA6 (by pulp-platform)

  7. fomu-workshop

    Support files for participating in a Fomu workshop

    Project mention: A programmable FPGA SoM in the tiny microSD form factor | news.ycombinator.com | 2024-11-19

    Thanks to RE the entire toolchain (formerly yosys) is open source for the lattice ICE40 [1] and they continue to add more fpga bitstreams like the ECP5.

    If anyone is looking for a cheap (~$15) and larger fpga board to tinker with, look no further than the ColorLight 5A-75b [2]

    [0] https://github.com/im-tomu/fomu-workshop/blob/master/docs/ri...

    [1] https://f4pga.org/

    [2] https://hackaday.com/2020/01/24/new-part-day-led-driver-is-f...

  8. RISC-V

    Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

  9. InfluxDB

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  10. airisc_core_complex

    Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

  11. fpga_riscv_cpu

    fpga verilog risc-v rv32i cpu

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Verilog Riscv discussion

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Verilog Riscv related posts

  • ARMv9 Architecture Helps Lift Arm to New Financial Heights

    1 project | news.ycombinator.com | 18 May 2025

  • Opensouce RISC-V CPU core implemented in Verilog from scratch in one night

    1 project | news.ycombinator.com | 16 Mar 2025

  • Wren6991/Hazard3: 3-stage RV32IMACZb* processor with debug

    5 projects | news.ycombinator.com | 10 Aug 2024

  • Hazard3

    1 project | news.ycombinator.com | 8 Aug 2024

  • Raspberry Pi Pico 2, our new $5 microcontroller board, on sale now

    2 projects | news.ycombinator.com | 8 Aug 2024

  • How many gates does a decent risc-v implementation take?

    2 projects | /r/RISCV | 16 Feb 2023

  • Open-source RISC-V CPU projects for contribution

    8 projects | /r/RISCV | 28 Jan 2023
  • A note from our sponsor - InfluxDB
    www.influxdata.com | 9 Jul 2025
    InfluxDB 3 OSS is now GA. Transform, enrich, and act on time series data directly in the database. Automate critical tasks and eliminate the need to move data externally. Download now. Learn more →

Index

What are some of the best open-source Riscv projects in Verilog? This list will help you:

# Project Stars
1 darkriscv 2,360
2 kianRiscV 914
3 Hazard3 884
4 riscv_vhdl 667
5 cheshire 271
6 fomu-workshop 164
7 RISC-V 95
8 airisc_core_complex 92
9 fpga_riscv_cpu 11

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