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Top 6 Verilog Riscv Projects
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WorkOS
The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.
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airisc_core_complex
Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
Project mention: Prototype Demonstration of a 32-bit RISC-V Softcore with FreeRTOS | /r/FPGA | 2023-06-03The project repository and the details about the paper can be found here.
NOTE:
The open source projects on this list are ordered by number of github stars.
The number of mentions indicates repo mentiontions in the last 12 Months or
since we started tracking (Dec 2020).
Verilog Riscv related posts
- How many gates does a decent risc-v implementation take?
- Open-source RISC-V CPU projects for contribution
- As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
- Need help learning how to use risc-v toolchain
- CPU DESIGN
- Where Lions Roam: RISC-V on the VELDT
- What is a list of all softcores that were designed purely using VHDL?
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A note from our sponsor - SaaSHub
www.saashub.com | 26 Apr 2024
Index
What are some of the best open-source Riscv projects in Verilog? This list will help you:
Project | Stars | |
---|---|---|
1 | darkriscv | 1,882 |
2 | riscv_vhdl | 578 |
3 | airisc_core_complex | 70 |
4 | Hazard3 | 70 |
5 | RISC-V | 42 |
6 | fpga_riscv_cpu | 8 |
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