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A tiny Open POWER ISA softcore written in VHDL 2008
My knee-jerk reaction was "No" since it's IBM POWER. But then I read that the POWER architecture and ISA support bi-endian, and then I also gather from https://github.com/antonblanchard/microwatt/search?p=1&q=endian that the microwatt starts up in little-endian (LE) mode. In addition, the examples are compiled for LE mode: https://github.com/antonblanchard/microwatt/blob/e40e752b9ab602f5ce1eb79be1fe96932558830d/hello_world/Makefile#L12
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
Access the most powerful time series database as a service. Ingest, store, & analyze all types of time series data in a fully-managed, purpose-built database. Keep data forever with low-cost storage and superior data compression.
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
I used this one https://github.com/lxp32/lxp32-cpu as base for building a RISC-V softcore.
Looking for help with RISC-V softcore and VHDL
3 projects | reddit.com/r/FPGA | 20 Apr 2022
Show HN: Soft-core RISC-V SoC with gdb support
2 projects | news.ycombinator.com | 31 May 2021
Recommendations for RISC-V on FPGA
7 projects | reddit.com/r/FPGA | 8 Mar 2023
How Much Would It Cost For A Truly Open Source RISC-V SOC?
5 projects | reddit.com/r/RISCV | 14 Jan 2023
Which FPGA for getting into RISC-V?
2 projects | reddit.com/r/RISCV | 1 Dec 2022