darkriscv
friscv
| darkriscv | friscv | |
|---|---|---|
| 3 | 1 | |
| 2,061 | 16 | |
| 3.3% | - | |
| 8.4 | 7.7 | |
| 6 days ago | 3 months ago | |
| Verilog | Coq | |
| BSD 3-clause "New" or "Revised" License | MIT License |
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darkriscv
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
friscv
What are some alternatives?
biriscv - 32-bit Superscalar RISC-V CPU
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
XiangShan - Open-source high-performance RISC-V processor
ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
riscv - RISC-V CPU Core (RV32IM)
rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
Cores-VeeR-EH1 - VeeR EH1 core
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.
fpga_riscv_cpu - fpga verilog risc-v rv32i cpu