darkriscv VS VexRiscv

Compare darkriscv vs VexRiscv and see what are their differences.


opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)


A FPGA friendly 32 bit RISC-V CPU implementation (by SpinalHDL)
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darkriscv VexRiscv
3 18
1,626 1,902
1.0% 1.8%
5.2 3.2
5 months ago 11 days ago
Verilog Assembly
BSD 3-clause "New" or "Revised" License MIT License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.


Posts with mentions or reviews of darkriscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-08-20.


Posts with mentions or reviews of VexRiscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-01-14.
  • How Much Would It Cost For A Truly Open Source RISC-V SOC?
    5 projects | reddit.com/r/RISCV | 14 Jan 2023
    If you use LiteX to generate a VexRiscV system-on-a-chip, you can include an open source DDR DRAM PHY. This works on Xilinx Spartan-6, Spartan7Artix7/Kintex7/Virtex7 FPGAs, and Lattice ECP5 FPGAs. DDR/LPDDR/DDR2/DDR3 depending on the FPGA.
  • Which FPGA for getting into RISC-V?
    2 projects | reddit.com/r/RISCV | 1 Dec 2022
    Something like https://github.com/SpinalHDL/VexRiscv will take far fewer
  • Looking for a suitable open-source RISC-V for an embedded project
    5 projects | reddit.com/r/FPGA | 4 Jul 2022
    4) https://github.com/SpinalHDL/VexRiscv
  • What do think of Chisel HDL? is it worth learning over Verilog/SystemVerilog?
    4 projects | reddit.com/r/FPGA | 29 Jun 2022
    I really like Chisel HDL or any other new HDL languages like SpinalHDL or migen b/c it allows you to create some very complex yet modular designs. See VexRiscv or LiteX for instance. Languages like this exist b/c there is a need for it, but I wouldn't say that you should learn these new languages over verilog. All these languages output verilog/VHDL for now, but there is work being to done eliminate the need for outputting verilog; eventually, Chisel will output an open source CIRCT IR. Hope is to get EDA vendors to support this IR which I'm sure will take a while. For now, you should definitely learn Verilog or VHDL before Chisel.
  • Looking for help with RISC-V softcore and VHDL
    3 projects | reddit.com/r/FPGA | 20 Apr 2022
  • Are there any dual-GBE, PoE-capable SBCs?
    2 projects | reddit.com/r/linuxhardware | 20 Aug 2021
  • Tips on building a RISC-V processor on FPGA
    5 projects | reddit.com/r/RISCV | 15 Jun 2021
  • Show HN: Soft-core RISC-V SoC with gdb support
    2 projects | news.ycombinator.com | 31 May 2021
    The SmallAndProductive configuration can be found here: https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/s....

    It’s a basic R32I configuration, without traps or branch prediction enabled, but with 5 pipeline stages and all bypass paths included, so it executes straight code at 1 instruction per clock.

    The VexRiscv also comes with a bunch of SOCs etc.

    The amazing thing about the VexRiscv is that it is configurable to the extreme and it’s extremely easy to do so. There are tons of other configurations in the same directory. It’d be trivial to create one that has the same configuration as this one and compare.

    SpinalHDL supports both Verilog and VHDL output, so you’re covered there as well.

    It’s not native VHDL, of course, so if you want to understand the code at the VHDL level instead of just wanting to use a soft core CPU, it’s probably not for you.

    That said, the VexRiscv design methodology is pretty amazing as well. I wrote about it here:

  • Weird altera issue
    2 projects | reddit.com/r/FPGA | 23 May 2021
    I'm trying to put the Murax SoC inside a DECA board from Arrow but I'm facing something quite odd. Along with the SoC, I'm adding a heartbeat LED just in case to see if everything is running and what I'm seeing is that when I try to constraint the jtag pins, starting by the TDI (Y5) on the SDC file, the bitstream programmed in the board makes the heartbeat LED to stop blink (it stucks on forever). In the beginning, I was thinking that would be something related to the voltage but as the pins C5-LED and Y5-TDI are from different banks, it doesn't make any sense....is there something I'm missing from here?
    9 projects | reddit.com/r/FPGA | 5 Apr 2021
    For expected hardware utilization you can look up existing implementations with similar features. E.g. VexRiscv

What are some alternatives?

When comparing darkriscv and VexRiscv you can also consider the following projects:

neorv32 - 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

biriscv - 32-bit Superscalar RISC-V CPU

RISCV-FiveStage - Marginally better than redstone

XiangShan - Open-source high-performance RISC-V processor

wb2axip - Bus bridges and other odds and ends

dromajo - RISC-V RV64GC emulator designed for RTL co-simulation

sdspi - SD-Card controller, using a SPI interface that is (optionally) shared

Cores-VeeR-EH1 - VeeR EH1 core


riscv - RISC-V CPU Core (RV32IM)

Rudi-RV32I - A rudimental RISCV CPU supporting RV32I instructions, in VHDL