darkriscv VS VexRiscv

Compare darkriscv vs VexRiscv and see what are their differences.

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation (by SpinalHDL)
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darkriscv VexRiscv
3 21
1,929 2,309
1.9% 2.2%
6.2 7.0
14 days ago 2 days ago
Verilog Assembly
BSD 3-clause "New" or "Revised" License MIT License
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

darkriscv

Posts with mentions or reviews of darkriscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-08-20.

VexRiscv

Posts with mentions or reviews of VexRiscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-10-23.
  • Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide
    4 projects | /r/RISCV | 23 Oct 2023
    With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.
  • RISC-V with AXI Peripheral
    2 projects | /r/FPGA | 20 Jun 2023
  • Intel discontinues Nios II IP
    3 projects | /r/FPGA | 14 Jun 2023
    I don't get what's going on with licensing and device support. I'm missing something here perhaps, but we use Cyclone 10 GX onwards and Quartus Pro so I don't have enough context maybe. Have you considered swapping your Nios ii to a VexRISCV as a side note? At ~1 Dhrystone MIPS/MHz it's roughly double that of the Nios V, for very few resources. All open source too. None of the migration documentation support though, so I can't judge how hard it would be.
  • How Much Would It Cost For A Truly Open Source RISC-V SOC?
    5 projects | /r/RISCV | 14 Jan 2023
    If you use LiteX to generate a VexRiscV system-on-a-chip, you can include an open source DDR DRAM PHY. This works on Xilinx Spartan-6, Spartan7Artix7/Kintex7/Virtex7 FPGAs, and Lattice ECP5 FPGAs. DDR/LPDDR/DDR2/DDR3 depending on the FPGA.
  • Which FPGA for getting into RISC-V?
    2 projects | /r/RISCV | 1 Dec 2022
    Something like https://github.com/SpinalHDL/VexRiscv will take far fewer
  • Faster CRC32-C on x86
    1 project | news.ycombinator.com | 1 Aug 2022
    A CPU built around the Gentoo philosophy would look like https://github.com/SpinalHDL/VexRiscv ;). Don't want an MMU? Fine. Need a larger RAM interface? You got it. Barrel ALU for DSP? Sure.

    Interpreted languages work by consolidating all of the optimization effort in the interpreter. This is similar to how CPUs work now, instead of extremely specific optimizations that are hard to create distributed among all code we use very general optimizations that push the limits of mathematics that is centralized in a CPU.

    -----

    Itanium had a lot of contemporary issues that made it not work. I would certainly blame Intel's business practices and reputation for a large part of it. There are likely niches for such processors. The VLIW is useful for DSP or graphics. Indeed, the only extant VLIW (that I know of) processor is the Russian Elbrus. I think the VLIW is only included to let them reuse a lot of the core logic of the CPU to drive a DSP engine, useful for radar and scientific simulation, though the sci sim would probably use commercial hardware which would be faster.

    It works on GPUs because they're doing DSP, basically. We could have weirder topologies for GPUs however, like a massive string of ALUs driven off an embedded core, so you try to kachunk all your data in a single clock domain after configuring the ALU string.

  • Looking for a suitable open-source RISC-V for an embedded project
    5 projects | /r/FPGA | 4 Jul 2022
    4) https://github.com/SpinalHDL/VexRiscv
  • What do think of Chisel HDL? is it worth learning over Verilog/SystemVerilog?
    4 projects | /r/FPGA | 29 Jun 2022
    I really like Chisel HDL or any other new HDL languages like SpinalHDL or migen b/c it allows you to create some very complex yet modular designs. See VexRiscv or LiteX for instance. Languages like this exist b/c there is a need for it, but I wouldn't say that you should learn these new languages over verilog. All these languages output verilog/VHDL for now, but there is work being to done eliminate the need for outputting verilog; eventually, Chisel will output an open source CIRCT IR. Hope is to get EDA vendors to support this IR which I'm sure will take a while. For now, you should definitely learn Verilog or VHDL before Chisel.
  • Looking for help with RISC-V softcore and VHDL
    3 projects | /r/FPGA | 20 Apr 2022
  • Thermal sensor mlx90640 with Nexys 3 fpga
    1 project | /r/FPGA | 16 Jan 2022
    I'd recommend giving vexriscv a look. It'll handily fit on your FPGA, leaving plants of room for I2C, VGA output, and whatever multiplication you end up wanting to do. It's very easy to get set up, and their example "briey" SOC even has VGA output already, but not hardware I2C (though you could easily bitbang it with the core). Adding in I2C via a "plugin" should be trivial.

What are some alternatives?

When comparing darkriscv and VexRiscv you can also consider the following projects:

biriscv - 32-bit Superscalar RISC-V CPU

neorv32 - :desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

XiangShan - Open-source high-performance RISC-V processor

ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

riscv - RISC-V CPU Core (RV32IM)

RISCV-FiveStage - Marginally better than redstone

Cores-VeeR-EH1 - VeeR EH1 core

wb2axip - Bus bridges and other odds and ends

friscv - RISCV CPU implementation in SystemVerilog

riscv-tests

meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture

dromajo - RISC-V RV64GC emulator designed for RTL co-simulation

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