darkriscv VS VexRiscv

Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.

If you use LiteX to generate a VexRiscV system-on-a-chip, you can include an open source DDR DRAM PHY. This works on Xilinx Spartan-6, Spartan7Artix7/Kintex7/Virtex7 FPGAs, and Lattice ECP5 FPGAs. DDR/LPDDR/DDR2/DDR3 depending on the FPGA.

Something like https://github.com/SpinalHDL/VexRiscv will take far fewer

4) https://github.com/SpinalHDL/VexRiscv

I really like Chisel HDL or any other new HDL languages like SpinalHDL or migen b/c it allows you to create some very complex yet modular designs. See VexRiscv or LiteX for instance. Languages like this exist b/c there is a need for it, but I wouldn't say that you should learn these new languages over verilog. All these languages output verilog/VHDL for now, but there is work being to done eliminate the need for outputting verilog; eventually, Chisel will output an open source CIRCT IR. Hope is to get EDA vendors to support this IR which I'm sure will take a while. For now, you should definitely learn Verilog or VHDL before Chisel.

The SmallAndProductive configuration can be found here: https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/s....

It’s a basic R32I configuration, without traps or branch prediction enabled, but with 5 pipeline stages and all bypass paths included, so it executes straight code at 1 instruction per clock.

The VexRiscv also comes with a bunch of SOCs etc.

The amazing thing about the VexRiscv is that it is configurable to the extreme and it’s extremely easy to do so. There are tons of other configurations in the same directory. It’d be trivial to create one that has the same configuration as this one and compare.

SpinalHDL supports both Verilog and VHDL output, so you’re covered there as well.

It’s not native VHDL, of course, so if you want to understand the code at the VHDL level instead of just wanting to use a soft core CPU, it’s probably not for you.

That said, the VexRiscv design methodology is pretty amazing as well. I wrote about it here:

I'm trying to put the Murax SoC inside a DECA board from Arrow but I'm facing something quite odd. Along with the SoC, I'm adding a heartbeat LED just in case to see if everything is running and what I'm seeing is that when I try to constraint the jtag pins, starting by the TDI (Y5) on the SDC file, the bitstream programmed in the board makes the heartbeat LED to stop blink (it stucks on forever). In the beginning, I was thinking that would be something related to the voltage but as the pins C5-LED and Y5-TDI are from different banks, it doesn't make any sense....is there something I'm missing from here?

For expected hardware utilization you can look up existing implementations with similar features. E.g. VexRiscv