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Are there any dual-GBE, PoE-capable SBCs?
2 projects | reddit.com/r/linuxhardware | 20 Aug 2021
Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
5 projects | reddit.com/r/linux | 26 Jun 2021
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
New to embedded
3 projects | reddit.com/r/embeddedlinux | 11 Mar 2023
There does exist a Yocto recipe for RISC-V that claims to support both 32 and 64-bit. I haven't used it myself, but your best bet may be spin up a custom Yocto/OE based distro. You can find the source and documentation here: https://github.com/riscv/meta-riscv
Pine64 August update: RISC and reward
2 projects | reddit.com/r/RISCV | 28 Aug 2022
Great news !. We have a yocto port for JH7110 here https://github.com/riscv/meta-riscv/blob/master/conf/machine/visionfive.conf, I will be happy to add a machine conf for pine64, It should be easy enough to start from above as template.
What are some alternatives?
biriscv - 32-bit Superscalar RISC-V CPU
XiangShan - Open-source high-performance RISC-V processor
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
Cores-VeeR-EH1 - VeeR EH1 core
riscv - RISC-V CPU Core (RV32IM)
friscv - RISCV CPU implementation in SystemVerilog
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.
meta-balena - A collection of Yocto layers used to build balenaOS images
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
ready-set-yocto - A short, unofficial guide on getting started with Yocto using a Raspberry Pi
ice-chips-verilog - IceChips is a library of all common discrete logic devices in Verilog