darkriscv VS meta-riscv

Compare darkriscv vs meta-riscv and see what are their differences.


opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)


OpenEmbedded/Yocto layer for RISC-V Architecture (by riscv)
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darkriscv meta-riscv
3 3
1,626 275
1.0% 2.2%
5.2 6.8
5 months ago about 2 months ago
Verilog BitBake
BSD 3-clause "New" or "Revised" License GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.


Posts with mentions or reviews of darkriscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-08-20.


Posts with mentions or reviews of meta-riscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-03-11.
  • New to embedded
    3 projects | reddit.com/r/embeddedlinux | 11 Mar 2023
    There does exist a Yocto recipe for RISC-V that claims to support both 32 and 64-bit. I haven't used it myself, but your best bet may be spin up a custom Yocto/OE based distro. You can find the source and documentation here: https://github.com/riscv/meta-riscv
  • Pine64 August update: RISC and reward
    2 projects | reddit.com/r/RISCV | 28 Aug 2022
    Great news !. We have a yocto port for JH7110 here https://github.com/riscv/meta-riscv/blob/master/conf/machine/visionfive.conf, I will be happy to add a machine conf for pine64, It should be easy enough to start from above as template.

What are some alternatives?

When comparing darkriscv and meta-riscv you can also consider the following projects:

biriscv - 32-bit Superscalar RISC-V CPU

XiangShan - Open-source high-performance RISC-V processor

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

Cores-VeeR-EH1 - VeeR EH1 core

riscv - RISC-V CPU Core (RV32IM)

friscv - RISCV CPU implementation in SystemVerilog

f4pga-examples - Example designs showing different ways to use F4PGA toolchains.

meta-balena - A collection of Yocto layers used to build balenaOS images

scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog

open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

ready-set-yocto - A short, unofficial guide on getting started with Yocto using a Raspberry Pi

ice-chips-verilog - IceChips is a library of all common discrete logic devices in Verilog