scr1 VS riscv-simple-sv

Compare scr1 vs riscv-simple-sv and see what are their differences.

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog (by syntacore)
Riscv risc-v Rtl Verilog Rv32i rv32e rv32imc rv32emc IP Core
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riscv-simple-sv

A simple RISC V core for teaching (by tilk)
risc-v Riscv Verilog
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scr1 riscv-simple-sv
2 2
768 145
2.3% -
3.3 0.0
9 days ago over 2 years ago
SystemVerilog SystemVerilog
GNU General Public License v3.0 or later BSD 3-clause "New" or "Revised" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

scr1

Posts with mentions or reviews of scr1. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-07-04.

riscv-simple-sv

Posts with mentions or reviews of riscv-simple-sv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-04-10.
  • Simple CPU cores to study?
    3 projects | /r/Verilog | 10 Apr 2021
    I published the code on GitHub: https://github.com/tilk/riscv-simple-sv
  • Need help in CPU design
    5 projects | /r/FPGA | 22 Mar 2021
    I need to run a RISC-V softcore in my FPGA. I don't need to develop the core myself, which means I can use one with good support and that is well implemented (if someone knows a good one, tell me in the comments, please). Since I'm a little new to this area I started by using a simple core: https://github.com/tilk/riscv-simple-sv, however, I'm a little lost in the steps that I need to do. First, I need to put the core in my FPGA. Then, how can I execute code in the core? Do I need to put the machine code into the ROM? And how can I do that? What if I want to debug my C programs that are supposed to run on the core?

What are some alternatives?

When comparing scr1 and riscv-simple-sv you can also consider the following projects:

FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA

cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

friscv - RISCV CPU implementation in SystemVerilog

gdb-stub - gdb-proxy implementation for bonfire

clic - RISC-V fast interrupt controller

picoMIPS - picoMIPS processor doing affine transformation

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Cores-VeeR-EL2 - VeeR EL2 Core

VeriGPU - OpenSource GPU, in Verilog, loosely based on RISC-V ISA

ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

rhd - Tiny 16-bit RISC Core

scr1 vs FPGA-Video-Processing riscv-simple-sv vs cv32e40p scr1 vs friscv riscv-simple-sv vs gdb-stub scr1 vs clic riscv-simple-sv vs picoMIPS scr1 vs VexRiscv riscv-simple-sv vs neorv32 scr1 vs Cores-VeeR-EL2 riscv-simple-sv vs VeriGPU scr1 vs ibex riscv-simple-sv vs rhd