SystemVerilog rv32e

Open-source SystemVerilog projects categorized as rv32e
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Topics: Core IP risc-v Verilog Riscv
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SystemVerilog rv32e Projects

  • scr1

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

  • WorkOS

    The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

    WorkOS logo
NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Index

Project Stars
1 scr1 775

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