scr1
Cores-VeeR-EL2
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| scr1 | Cores-VeeR-EL2 | |
|---|---|---|
| 2 | 1 | |
| 775 | 220 | |
| 3.2% | 4.1% | |
| 3.0 | 9.2 | |
| 19 days ago | 11 days ago | |
| SystemVerilog | SystemVerilog | |
| GNU General Public License v3.0 or later | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
scr1
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Looking for a suitable open-source RISC-V for an embedded project
Would this be suitable? https://github.com/syntacore/scr1 I haven't used it, but I saw it in Riscduino project which continues to appear in Open MPWs.
- Mikron MIK32 – Made in Russia 32-bit RISC-V MCU... for about $6
Cores-VeeR-EL2
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Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
Including Western Digital's cores used in their SSD controllers: https://github.com/chipsalliance/Cores-SweRV https://github.com/chipsalliance/Cores-SweRV-EL2
What are some alternatives?
riscv-simple-sv - A simple RISC V core for teaching
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA
Cores-VeeR-EH1 - VeeR EH1 core
friscv - RISCV CPU implementation in SystemVerilog
projf-explore - Project F brings FPGAs to life with exciting open-source designs you can build on.
clic - RISC-V fast interrupt controller
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
rocket-chip - Rocket Chip Generator
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
VeriGPU - OpenSource GPU, in Verilog, loosely based on RISC-V ISA