SystemVerilog Axi4

Open-source SystemVerilog projects categorized as Axi4
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Top 6 SystemVerilog Axi4 Projects

Axi4

  1. axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  2. InfluxDB

    InfluxDB – Built for High-Performance Time Series Workloads. InfluxDB 3 OSS is now GA. Transform, enrich, and act on time series data directly in the database. Automate critical tasks and eliminate the need to move data externally. Download now.

    InfluxDB logo

  3. Cores-VeeR-EH1

    VeeR EH1 core

  4. Cores-VeeR-EL2

    VeeR EL2 Core

  5. ravenoc

    RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

  6. friscv

    RISCV CPU implementation in SystemVerilog

  7. rggen-sv-rtl

    Common SystemVerilog RTL modules for RgGen

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

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Index

What are some of the best open-source Axi4 projects in SystemVerilog? This list will help you:

# Project Stars
1 axi 1,274
2 Cores-VeeR-EH1 848
3 Cores-VeeR-EL2 275
4 ravenoc 166
5 friscv 26
6 rggen-sv-rtl 12

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InfluxDB 3 OSS is now GA. Transform, enrich, and act on time series data directly in the database. Automate critical tasks and eliminate the need to move data externally. Download now.
www.influxdata.com
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