SystemVerilog Axi4

Open-source SystemVerilog projects categorized as Axi4

Top 5 SystemVerilog Axi4 Projects

  • axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  • Cores-VeeR-EH1

    VeeR EH1 core

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

    InfluxDB logo
  • Cores-VeeR-EL2

    VeeR EL2 Core

  • ravenoc

    RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications

  • rggen-sv-rtl

    Common SystemVerilog RTL modules for RgGen

  • WorkOS

    The modern identity platform for B2B SaaS. The APIs are flexible and easy-to-use, supporting authentication, user identity, and complex enterprise features like SSO and SCIM provisioning.

    WorkOS logo
NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Index

What are some of the best open-source Axi4 projects in SystemVerilog? This list will help you:

Project Stars
1 axi 920
2 Cores-VeeR-EH1 773
3 Cores-VeeR-EL2 222
4 ravenoc 121
5 rggen-sv-rtl 10
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