SystemVerilog asic-design

Open-source SystemVerilog projects categorized as asic-design
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Topics: risc-v Processor Riscv Fpga Rtl
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Top 3 SystemVerilog asic-design Projects

  • Cores-VeeR-EH1

    VeeR EH1 core

  • VeriGPU

    OpenSource GPU, in Verilog, loosely based on RISC-V ISA

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

    InfluxDB logo

  • Cores-VeeR-EL2

    VeeR EL2 Core

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

SystemVerilog asic-design related posts

Index

What are some of the best open-source asic-design projects in SystemVerilog? This list will help you:

Project Stars
1 Cores-VeeR-EH1 773
2 VeriGPU 484
3 Cores-VeeR-EL2 222

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