Cores-VeeR-EL2
cv32e40p
| Cores-VeeR-EL2 | cv32e40p | |
|---|---|---|
| 1 | 3 | |
| 222 | 874 | |
| 0.9% | 1.5% | |
| 9.0 | 8.9 | |
| 4 days ago | 10 days ago | |
| SystemVerilog | SystemVerilog | |
| Apache License 2.0 | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Cores-VeeR-EL2
-
Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
Including Western Digital's cores used in their SSD controllers: https://github.com/chipsalliance/Cores-SweRV https://github.com/chipsalliance/Cores-SweRV-EL2
cv32e40p
-
ALU CIRCUIT DESIGN LEVEL VS RTL LEVEL
For a high performance CPU I would expect the second approach, eventually using RTL only to connect the single blocks like adders, shifters, comparators etc... but looking at some projects available on GitHub (for example Pulp RISC-V CPU https://github.com/openhwgroup/cv32e40p/blob/master/rtl/cv32e40p_alu.sv) the ALU is always fully coded in RTL.
- Are FPGAs the best choice for this project?
-
2 questions after finishing digital logic
Here is an example of a GitHub repository for a riscv core I found on google: https://github.com/openhwgroup/cv32e40p/tree/master/rtl
What are some alternatives?
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Cores-VeeR-EH1 - VeeR EH1 core
riscv-simple-sv - A simple RISC V core for teaching
projf-explore - Project F brings FPGAs to life with exciting open-source designs you can build on.
capstone - Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings. [Moved to: https://github.com/capstone-engine/capstone]
rocket-chip - Rocket Chip Generator
VeriGPU - OpenSource GPU, in Verilog, loosely based on RISC-V ISA
friscv - RISCV CPU implementation in SystemVerilog
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
WDMC-Ex2-Ultra - Enhanced Ram Disk and Linux Kernel for WD My Cloud Ex2 Ultra