ALU CIRCUIT DESIGN LEVEL VS RTL LEVEL

• cv32e40p

  3 874 8.9 SystemVerilog

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  

For a high performance CPU I would expect the second approach, eventually using RTL only to connect the single blocks like adders, shifters, comparators etc... but looking at some projects available on GitHub (for example Pulp RISC-V CPU https://github.com/openhwgroup/cv32e40p/blob/master/rtl/cv32e40p_alu.sv) the ALU is always fully coded in RTL.

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