cv32e40p
friscv
| cv32e40p | friscv | |
|---|---|---|
| 3 | 1 | |
| 874 | 15 | |
| 1.5% | - | |
| 8.9 | 7.7 | |
| 6 days ago | 7 days ago | |
| SystemVerilog | Coq | |
| GNU General Public License v3.0 or later | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
cv32e40p
-
ALU CIRCUIT DESIGN LEVEL VS RTL LEVEL
For a high performance CPU I would expect the second approach, eventually using RTL only to connect the single blocks like adders, shifters, comparators etc... but looking at some projects available on GitHub (for example Pulp RISC-V CPU https://github.com/openhwgroup/cv32e40p/blob/master/rtl/cv32e40p_alu.sv) the ALU is always fully coded in RTL.
- Are FPGAs the best choice for this project?
-
2 questions after finishing digital logic
Here is an example of a GitHub repository for a riscv core I found on google: https://github.com/openhwgroup/cv32e40p/tree/master/rtl
friscv
What are some alternatives?
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
riscv-simple-sv - A simple RISC V core for teaching
ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
Cores-VeeR-EL2 - VeeR EL2 Core
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
capstone - Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings. [Moved to: https://github.com/capstone-engine/capstone]
cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
Cores-VeeR-EH1 - VeeR EH1 core
rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
airisc_core_complex - Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.