cv32e40p VS riscv-simple-sv

For a high performance CPU I would expect the second approach, eventually using RTL only to connect the single blocks like adders, shifters, comparators etc... but looking at some projects available on GitHub (for example Pulp RISC-V CPU https://github.com/openhwgroup/cv32e40p/blob/master/rtl/cv32e40p_alu.sv) the ALU is always fully coded in RTL.

Here is an example of a GitHub repository for a riscv core I found on google: https://github.com/openhwgroup/cv32e40p/tree/master/rtl

I published the code on GitHub: https://github.com/tilk/riscv-simple-sv

I need to run a RISC-V softcore in my FPGA. I don't need to develop the core myself, which means I can use one with good support and that is well implemented (if someone knows a good one, tell me in the comments, please). Since I'm a little new to this area I started by using a simple core: https://github.com/tilk/riscv-simple-sv, however, I'm a little lost in the steps that I need to do. First, I need to put the core in my FPGA. Then, how can I execute code in the core? Do I need to put the machine code into the ROM? And how can I do that? What if I want to debug my C programs that are supposed to run on the core?