riscv-simple-sv VS neorv32

Compare riscv-simple-sv vs neorv32 and see what are their differences.

riscv-simple-sv

A simple RISC V core for teaching (by tilk)
risc-v Riscv Verilog
Source Code
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neorv32

:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. (by stnolting)
risc-v soft-core Vhdl Fpga soc Microcontroller Processor Cpu Riscv system-on-chip openocd Embedded rv32 neorv32 Verilog GDB Asic Safety
Source Code
neorv32.org
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riscv-simple-sv neorv32
2 77
145 1,423
- -
0.0 9.9
over 2 years ago 7 days ago
SystemVerilog C
BSD 3-clause "New" or "Revised" License BSD 3-clause "New" or "Revised" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

riscv-simple-sv

Posts with mentions or reviews of riscv-simple-sv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-04-10.
  • Simple CPU cores to study?
    3 projects | /r/Verilog | 10 Apr 2021
    I published the code on GitHub: https://github.com/tilk/riscv-simple-sv
  • Need help in CPU design
    5 projects | /r/FPGA | 22 Mar 2021
    I need to run a RISC-V softcore in my FPGA. I don't need to develop the core myself, which means I can use one with good support and that is well implemented (if someone knows a good one, tell me in the comments, please). Since I'm a little new to this area I started by using a simple core: https://github.com/tilk/riscv-simple-sv, however, I'm a little lost in the steps that I need to do. First, I need to put the core in my FPGA. Then, how can I execute code in the core? Do I need to put the machine code into the ROM? And how can I do that? What if I want to debug my C programs that are supposed to run on the core?

neorv32

Posts with mentions or reviews of neorv32. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-03-08.

What are some alternatives?

When comparing riscv-simple-sv and neorv32 you can also consider the following projects:

cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog

linux-on-litex-vexriscv - Linux on LiteX-VexRiscv

gdb-stub - gdb-proxy implementation for bonfire

picoMIPS - picoMIPS processor doing affine transformation

upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

VeriGPU - OpenSource GPU, in Verilog, loosely based on RISC-V ISA

chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

rhd - Tiny 16-bit RISC Core

lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

riscv-simple-sv vs cv32e40p neorv32 vs VexRiscv riscv-simple-sv vs scr1 neorv32 vs linux-on-litex-vexriscv riscv-simple-sv vs gdb-stub neorv32 vs picoMIPS riscv-simple-sv vs picoMIPS neorv32 vs upduino-projects riscv-simple-sv vs VeriGPU neorv32 vs chipyard riscv-simple-sv vs rhd neorv32 vs lxp32-cpu