riscv-simple-sv

A simple RISC V core for teaching (by tilk)

Riscv-simple-sv Alternatives

Similar projects and alternatives to riscv-simple-sv

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better riscv-simple-sv alternative or higher similarity.

riscv-simple-sv reviews and mentions

Posts with mentions or reviews of riscv-simple-sv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-04-10.
  • Simple CPU cores to study?
    3 projects | /r/Verilog | 10 Apr 2021
    I published the code on GitHub: https://github.com/tilk/riscv-simple-sv
  • Need help in CPU design
    5 projects | /r/FPGA | 22 Mar 2021
    I need to run a RISC-V softcore in my FPGA. I don't need to develop the core myself, which means I can use one with good support and that is well implemented (if someone knows a good one, tell me in the comments, please). Since I'm a little new to this area I started by using a simple core: https://github.com/tilk/riscv-simple-sv, however, I'm a little lost in the steps that I need to do. First, I need to put the core in my FPGA. Then, how can I execute code in the core? Do I need to put the machine code into the ROM? And how can I do that? What if I want to debug my C programs that are supposed to run on the core?

Stats

Basic riscv-simple-sv repo stats
2
145
0.0
over 2 years ago
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