riscv-simple-sv VS cv32e40p

Compare riscv-simple-sv vs cv32e40p and see what are their differences.

riscv-simple-sv

A simple RISC V core for teaching (by tilk)
risc-v Riscv Verilog
Source Code
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cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform (by openhwgroup)
Riscv riscv32imfc
Source Code
docs.openhwgroup.org
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riscv-simple-sv cv32e40p
2 3
145 874
- 1.5%
0.0 8.9
over 2 years ago 13 days ago
SystemVerilog SystemVerilog
BSD 3-clause "New" or "Revised" License GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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riscv-simple-sv

Posts with mentions or reviews of riscv-simple-sv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-04-10.
  • Simple CPU cores to study?
    3 projects | /r/Verilog | 10 Apr 2021
    I published the code on GitHub: https://github.com/tilk/riscv-simple-sv
  • Need help in CPU design
    5 projects | /r/FPGA | 22 Mar 2021
    I need to run a RISC-V softcore in my FPGA. I don't need to develop the core myself, which means I can use one with good support and that is well implemented (if someone knows a good one, tell me in the comments, please). Since I'm a little new to this area I started by using a simple core: https://github.com/tilk/riscv-simple-sv, however, I'm a little lost in the steps that I need to do. First, I need to put the core in my FPGA. Then, how can I execute code in the core? Do I need to put the machine code into the ROM? And how can I do that? What if I want to debug my C programs that are supposed to run on the core?

cv32e40p

Posts with mentions or reviews of cv32e40p. We have used some of these posts to build our list of alternatives and similar projects.

What are some alternatives?

When comparing riscv-simple-sv and cv32e40p you can also consider the following projects:

scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog

cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

gdb-stub - gdb-proxy implementation for bonfire

Cores-VeeR-EL2 - VeeR EL2 Core

picoMIPS - picoMIPS processor doing affine transformation

capstone - Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings. [Moved to: https://github.com/capstone-engine/capstone]

neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Cores-VeeR-EH1 - VeeR EH1 core

VeriGPU - OpenSource GPU, in Verilog, loosely based on RISC-V ISA

friscv - RISCV CPU implementation in SystemVerilog

rhd - Tiny 16-bit RISC Core

FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA

riscv-simple-sv vs scr1 cv32e40p vs cva6 riscv-simple-sv vs gdb-stub cv32e40p vs Cores-VeeR-EL2 riscv-simple-sv vs picoMIPS cv32e40p vs capstone riscv-simple-sv vs neorv32 cv32e40p vs Cores-VeeR-EH1 riscv-simple-sv vs VeriGPU cv32e40p vs friscv riscv-simple-sv vs rhd riscv-simple-sv vs FPGA-Video-Processing