Need help in CPU design

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  • riscv-simple-sv

    A simple RISC V core for teaching

    I need to run a RISC-V softcore in my FPGA. I don't need to develop the core myself, which means I can use one with good support and that is well implemented (if someone knows a good one, tell me in the comments, please). Since I'm a little new to this area I started by using a simple core:, however, I'm a little lost in the steps that I need to do. First, I need to put the core in my FPGA. Then, how can I execute code in the core? Do I need to put the machine code into the ROM? And how can I do that? What if I want to debug my C programs that are supposed to run on the core?

  • riscv_verilator_model

    RISCV model for Verilator/FPGA targets Good start...

  • SonarQube

    Static code analysis for 29 languages.. Your projects are multi-language. So is SonarQube analysis. Find Bugs, Vulnerabilities, Security Hotspots, and Code Smells so you can release quality code every time. Get started analyzing your projects today for free.

  • picoMIPS

    picoMIPS processor doing affine transformation

  • neorv32

    :desktop_computer: A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

    You don't say which language you want the core to be in. If you want VHDL then the NeoRV32 is a reasonable compromise between speed and resource usage. The Bonfire CPU is another option if you are looking for something with more performance at the cost of user friendliness.

  • gdb-stub

    gdb-proxy implementation for bonfire

    Regarding debug, very few open source cores support anything approaching the kind of debug interface you would find on a microcontroller or vendor core (breakpoints, single stepping and memory viewers). Supporting these features involves considerable extra hardware and some special software to interface with GDB, called a GDB stub. The Bonfire CPU has support for a GDB stub but I've never tried it.

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