SystemVerilog Fusesoc

Open-source SystemVerilog projects categorized as Fusesoc
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Topics: Fpga risc-v Processor Riscv Rtl
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Top 3 SystemVerilog Fusesoc Projects

  • Cores-VeeR-EH1

    VeeR EH1 core

  • Cores-VeeR-EL2

    VeeR EL2 Core

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

    InfluxDB logo

  • fpga_screensaver

    This project implements the VGA protocol and allows custom images to be displayed to the screen using the Sipeed Tang Nano FPGA dev board.

    • Project mention: Best fpga for begginers | /r/FPGA | 2023-06-09

    This is a simple VGA project I did for the Tang Nano: https://github.com/sifferman/fpga_screensaver

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Index

What are some of the best open-source Fusesoc projects in SystemVerilog? This list will help you:

Project Stars
1 Cores-VeeR-EH1 774
2 Cores-VeeR-EL2 222
3 fpga_screensaver 6

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