scr1
clic
Our great sponsors
scr1 | clic | |
---|---|---|
2 | 1 | |
763 | 15 | |
3.5% | - | |
3.3 | 4.3 | |
18 days ago | about 1 month ago | |
SystemVerilog | SystemVerilog | |
GNU General Public License v3.0 or later | Apache License 2.0 |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
scr1
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Looking for a suitable open-source RISC-V for an embedded project
Would this be suitable? https://github.com/syntacore/scr1 I haven't used it, but I saw it in Riscduino project which continues to appear in Open MPWs.
clic
We haven't tracked posts mentioning clic yet.
Tracking mentions began in Dec 2020.
What are some alternatives?
riscv-simple-sv - A simple RISC V core for teaching
FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA
friscv - RISCV CPU implementation in SystemVerilog
Cores-VeeR-EL2 - VeeR EL2 Core
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Cores-VeeR-EH1 - VeeR EH1 core
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
M2GL025-Creative-Board - Igloo2 M2GL025 Creative Development Board
VeriGPU - OpenSource GPU, in Verilog, loosely based on RISC-V ISA
core-v-cores - CORE-V Family of RISC-V Cores