filament
darkriscv
| filament | darkriscv | |
|---|---|---|
| 3 | 3 | |
| 129 | 1,905 | |
| 4.7% | 2.4% | |
| 8.7 | 6.3 | |
| 5 days ago | 3 days ago | |
| Verilog | Verilog | |
| MIT License | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
filament
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Engineer creates CPU from scratch in two weeks – begins work on GPUs
Verilog is kind of trash by modern standards. Unfortunately we are stuck with it (well SystemVerilog) until tool vendors support something else.
It's kind of a similar situation to JavaScript actually. And in a similar way, you can compile to Verilog, but just like with JS it makes debugging much more painful.
There was this interesting project but it seems inactive: https://llhd.io/
There's also various alternative HDLs that seem to have various levels of solving the wrong problem (SpinalHDL, MyHDL, Chisel). This one looks quite interesting though: https://filamenthdl.com/
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Filament – A Language for Fearless Hardware Design
It's under /apps in the repo: https://github.com/cucapra/filament/tree/f5da227a059f181b996...
darkriscv
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
What are some alternatives?
hdl - HDL libraries and projects
biriscv - 32-bit Superscalar RISC-V CPU
XiangShan - Open-source high-performance RISC-V processor
riscv - RISC-V CPU Core (RV32IM)
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
Cores-VeeR-EH1 - VeeR EH1 core
friscv - RISCV CPU implementation in SystemVerilog
meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.
open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
ice-chips-verilog - IceChips is a library of all common discrete logic devices in Verilog
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog