Verilog hardware-description-language Projects

filament

3 126 8.9 Verilog

Fearless hardware design (by cucapra)

Project mention: Engineer creates CPU from scratch in two weeks – begins work on GPUs | news.ycombinator.com | 2024-04-15

Verilog is kind of trash by modern standards. Unfortunately we are stuck with it (well SystemVerilog) until tool vendors support something else.
It's kind of a similar situation to JavaScript actually. And in a similar way, you can compile to Verilog, but just like with JS it makes debugging much more painful.
There was this interesting project but it seems inactive: https://llhd.io/
There's also various alternative HDLs that seem to have various levels of solving the wrong problem (SpinalHDL, MyHDL, Chisel). This one looks quite interesting though: https://filamenthdl.com/

InfluxDB

www.influxdata.com featured

Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Verilog hardware-description-language related posts

Engineer creates CPU from scratch in two weeks – begins work on GPUs

1 project | news.ycombinator.com | 15 Apr 2024
Check out this state machine reading+writing /dev/stdin and stdout from an FPGA to play a little guessing game at the console. Code in comments.

3 projects | /r/FPGA | 14 Jul 2021