Engineer creates CPU from scratch in two weeks – begins work on GPUs

• filament

  3 126 8.9 Verilog

  Fearless hardware design (by cucapra)

  

Verilog is kind of trash by modern standards. Unfortunately we are stuck with it (well SystemVerilog) until tool vendors support something else.

It's kind of a similar situation to JavaScript actually. And in a similar way, you can compile to Verilog, but just like with JS it makes debugging much more painful.

There was this interesting project but it seems inactive: https://llhd.io/

There's also various alternative HDLs that seem to have various levels of solving the wrong problem (SpinalHDL, MyHDL, Chisel). This one looks quite interesting though: https://filamenthdl.com/

• WorkOS

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