darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
open-fpga-verilog-tutorial
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools (by Obijuan)
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darkriscv | open-fpga-verilog-tutorial | |
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3 | 3 | |
1,882 | 743 | |
2.8% | - | |
6.3 | 0.0 | |
6 days ago | about 4 years ago | |
Verilog | Verilog | |
BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 only |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
darkriscv
Posts with mentions or reviews of darkriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-20.
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
open-fpga-verilog-tutorial
Posts with mentions or reviews of open-fpga-verilog-tutorial.
We have used some of these posts to build our list of alternatives
and similar projects.
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FPGA for beginners?
The toolchain is called Icestorm, main tool is yosys, most information will be in English. I started with this tutorials here (also in English) https://github.com/Obijuan/open-fpga-verilog-tutorial. Then I used books to learn more on the basics of cpu design in verilog (which can also found online). Obijuan is a Spanish profesor teaching digital electronics in university, he lead the development of a graphical user interface to generate verilog based on a blocks UI, which helps design circuits when you are starting, but unfortunately I believe all his videos are in Spanish, I'd suggest you give it a try even if you don't understand English, as the material available (wiki and videos) is very good. Look for "fpgawars jedi academy " and IceStudio (the tool). But in the end, I personally felt limited by the GUI tool (which was still under heavy development at the time) and went straight to code the verilog code by hand (which obviously is more flexible). Anyway I feel there are not that many pattern to know.
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What's the difference between FPGA, RISC-V, Arduino?
Among your choices, FPGA is the answer. I would suggest a cheap iCE40 board like the iCESugar, to get started. Then follow tutorials targetting ice40+open stack.
- Digital Design for FPGAs, with free tools
What are some alternatives?
When comparing darkriscv and open-fpga-verilog-tutorial you can also consider the following projects:
biriscv - 32-bit Superscalar RISC-V CPU
icestudio - :snowflake: Visual editor for open FPGA boards
XiangShan - Open-source high-performance RISC-V processor
apio - :seedling: Open source ecosystem for open FPGA boards
riscv - RISC-V CPU Core (RV32IM)
uhd - The USRP™ Hardware Driver Repository
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
NTHU-ICLAB - 清華大學 | 積體電路設計實驗 (IC LAB) | 110上
Cores-VeeR-EH1 - VeeR EH1 core
FPGA_Asynchronous_FIFO - FIFO implementation with different clock domains for read and write.
friscv - RISCV CPU implementation in SystemVerilog
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
darkriscv vs biriscv
open-fpga-verilog-tutorial vs icestudio
darkriscv vs XiangShan
open-fpga-verilog-tutorial vs apio
darkriscv vs riscv
open-fpga-verilog-tutorial vs uhd
darkriscv vs VexRiscv
open-fpga-verilog-tutorial vs NTHU-ICLAB
darkriscv vs Cores-VeeR-EH1
open-fpga-verilog-tutorial vs FPGA_Asynchronous_FIFO
darkriscv vs friscv
open-fpga-verilog-tutorial vs psram-tang-nano-9k