darkriscv VS open-fpga-verilog-tutorial

Compare darkriscv vs open-fpga-verilog-tutorial and see what are their differences.


opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)


Learn how to design digital systems and synthesize them into an FPGA using only opensource tools (by Obijuan)
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darkriscv open-fpga-verilog-tutorial
3 3
1,630 653
1.2% -
2.8 0.0
5 months ago about 3 years ago
Verilog Verilog
BSD 3-clause "New" or "Revised" License GNU General Public License v3.0 only
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.


Posts with mentions or reviews of darkriscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-08-20.


Posts with mentions or reviews of open-fpga-verilog-tutorial. We have used some of these posts to build our list of alternatives and similar projects.

We haven't tracked posts mentioning open-fpga-verilog-tutorial yet.
Tracking mentions began in Dec 2020.

What are some alternatives?

When comparing darkriscv and open-fpga-verilog-tutorial you can also consider the following projects:

biriscv - 32-bit Superscalar RISC-V CPU

XiangShan - Open-source high-performance RISC-V processor

icestudio - :snowflake: Visual editor for open FPGA boards

apio - :seedling: Open source ecosystem for open FPGA boards

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

uhd - The USRP™ Hardware Driver Repository

Cores-VeeR-EH1 - VeeR EH1 core

riscv - RISC-V CPU Core (RV32IM)

friscv - RISCV CPU implementation in SystemVerilog

FPGA_Asynchronous_FIFO - FIFO implementation with different clock domains for read and write.

f4pga-examples - Example designs showing different ways to use F4PGA toolchains.

meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture