darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
ice-chips-verilog
IceChips is a library of all common discrete logic devices in Verilog (by TimRudy)
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| darkriscv | ice-chips-verilog | |
|---|---|---|
| 3 | 4 | |
| 1,882 | 116 | |
| 2.8% | - | |
| 6.3 | 0.9 | |
| 6 days ago | about 1 year ago | |
| Verilog | Verilog | |
| BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 only |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
darkriscv
Posts with mentions or reviews of darkriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-20.
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
ice-chips-verilog
Posts with mentions or reviews of ice-chips-verilog.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-28.
- Software for the arrangement of computer components on breadboards
- Has anyone ever made a z80 out of 7400 series parts?
- I'm really interested in learning more about Verilog but I have no prior coding experience, what's some of the ways a beginner like me can learn more about Verilog and RTL designing in general ?
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Improving my homemade 32-bit RISC-V CPU made only out of discrete logic ICs
If you want to go to the next level I'd suggest recreating the CPU in Verilog and simulating it there. That will let you quickly run testbenches against the virtual version and stress test the logical design itself, which in turn would help rule out electrical problems. Here is a 74-series Verilog simulation library you could use to kickstart a Verilog simulation.
What are some alternatives?
When comparing darkriscv and ice-chips-verilog you can also consider the following projects:
biriscv - 32-bit Superscalar RISC-V CPU
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
XiangShan - Open-source high-performance RISC-V processor
fritzing-app - Fritzing desktop application
riscv - RISC-V CPU Core (RV32IM)
LS6502 - 6502 processor implemented in Logisim
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
CPLD-Guide - Complex Programmable Logic Device (CPLD) Guide
Cores-VeeR-EH1 - VeeR EH1 core
friscv - RISCV CPU implementation in SystemVerilog
meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture
f4pga-examples - Example designs showing different ways to use F4PGA toolchains.
darkriscv vs biriscv
ice-chips-verilog vs OpenTimer
darkriscv vs XiangShan
ice-chips-verilog vs fritzing-app
darkriscv vs riscv
ice-chips-verilog vs LS6502
darkriscv vs VexRiscv
ice-chips-verilog vs CPLD-Guide
darkriscv vs Cores-VeeR-EH1
darkriscv vs friscv
darkriscv vs meta-riscv
darkriscv vs f4pga-examples