darkriscv VS ice-chips-verilog

Compare darkriscv vs ice-chips-verilog and see what are their differences.

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
#Riscv #processor-design #Rv32i #rv32e #Verilog #risc-v #Fpga #Rtl #softcore #Core #Processor #Cpu
Source Code

ice-chips-verilog

IceChips is a library of all common discrete logic devices in Verilog (by TimRudy)
#7400 #verilog-components #eda #logic-circuit #Fpga #iverilog #open-hardware #digital-logic #icestorm
Source Code
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darkriscv ice-chips-verilog
3 2
1,626 103
1.0% -
5.2 0.0
5 months ago 3 months ago
Verilog Verilog
BSD 3-clause "New" or "Revised" License GNU General Public License v3.0 only
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

darkriscv

Posts with mentions or reviews of darkriscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-08-20.

ice-chips-verilog

Posts with mentions or reviews of ice-chips-verilog. We have used some of these posts to build our list of alternatives and similar projects.

We haven't tracked posts mentioning ice-chips-verilog yet.
Tracking mentions began in Dec 2020.

What are some alternatives?

When comparing darkriscv and ice-chips-verilog you can also consider the following projects:

biriscv - 32-bit Superscalar RISC-V CPU

XiangShan - Open-source high-performance RISC-V processor

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

Cores-VeeR-EH1 - VeeR EH1 core

riscv - RISC-V CPU Core (RV32IM)

friscv - RISCV CPU implementation in SystemVerilog

f4pga-examples - Example designs showing different ways to use F4PGA toolchains.

meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture

scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog

open-fpga-verilog-tutorial - Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems

Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog

darkriscv vs biriscv
darkriscv vs XiangShan
darkriscv vs VexRiscv
darkriscv vs Cores-VeeR-EH1
darkriscv vs riscv
darkriscv vs friscv
darkriscv vs f4pga-examples
darkriscv vs meta-riscv
darkriscv vs scr1
darkriscv vs open-fpga-verilog-tutorial
ice-chips-verilog vs OpenTimer
darkriscv vs Toast-RV32i