darkriscv VS f4pga-examples

Compare darkriscv vs f4pga-examples and see what are their differences.


opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)


Example designs showing different ways to use F4PGA toolchains. (by chipsalliance)
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darkriscv f4pga-examples
3 1
1,626 236
1.0% 1.7%
5.2 8.1
5 months ago about 2 months ago
Verilog Verilog
BSD 3-clause "New" or "Revised" License Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.


Posts with mentions or reviews of darkriscv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-08-20.


Posts with mentions or reviews of f4pga-examples. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-09-28.

What are some alternatives?

When comparing darkriscv and f4pga-examples you can also consider the following projects:

biriscv - 32-bit Superscalar RISC-V CPU

XiangShan - Open-source high-performance RISC-V processor

VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation

Cores-VeeR-EH1 - VeeR EH1 core

riscv - RISC-V CPU Core (RV32IM)

zipcpu - A small, light weight, RISC CPU soft core

prjxray - Documenting the Xilinx 7-series bit-stream format.

friscv - RISCV CPU implementation in SystemVerilog

meta-riscv - OpenEmbedded/Yocto layer for RISC-V Architecture

f4pga - FOSS Flow For FPGA

scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog

prjtrellis - Documenting the Lattice ECP5 bit-stream format.