spu32
Small Processing Unit 32: A compact RV32I CPU written in Verilog (by maikmerten)
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
| spu32 | darkriscv | |
|---|---|---|
| 1 | 3 | |
| 60 | 1,892 | |
| - | 1.7% | |
| 0.0 | 6.3 | |
| almost 2 years ago | 17 days ago | |
| C | Verilog | |
| MIT License | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
spu32
Posts with mentions or reviews of spu32.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-05-10.
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Designing instruction decoder
You asked for "elegant and simple". Disregarding your request, here's how I decode RISC-V: https://github.com/maikmerten/spu32/blob/master/cpu/decoder.v
darkriscv
Posts with mentions or reviews of darkriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-20.
-
As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
What are some alternatives?
When comparing spu32 and darkriscv you can also consider the following projects:
shecc - A self-hosting and educational C optimizing compiler
biriscv - 32-bit Superscalar RISC-V CPU
RISCV - A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i]
XiangShan - Open-source high-performance RISC-V processor
quasiSoC - No-MMU Linux capable RISC-V SoC designed to be useful.
riscv - RISC-V CPU Core (RV32IM)
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
esp - Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
Cores-VeeR-EH1 - VeeR EH1 core
cariboulite - CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
friscv - RISCV CPU implementation in SystemVerilog