spu32
quasiSoC
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| spu32 | quasiSoC | |
|---|---|---|
| 1 | 1 | |
| 60 | 91 | |
| - | - | |
| 0.0 | 6.4 | |
| almost 2 years ago | 4 days ago | |
| C | C | |
| MIT License | GNU General Public License v3.0 only |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
spu32
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Designing instruction decoder
You asked for "elegant and simple". Disregarding your request, here's how I decode RISC-V: https://github.com/maikmerten/spu32/blob/master/cpu/decoder.v
quasiSoC
What are some alternatives?
shecc - A self-hosting and educational C optimizing compiler
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
RISCV - A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i]
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
esp - Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
RVVM - The RISC-V Virtual Machine
cariboulite - CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
rt-thread - RT-Thread is an open source IoT real-time operating system (RTOS).
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
SAP1 - RTL Implementation of Malvino's SAP1. I was inspired to do this after seeing Ben Eater's Breadboard implementation